Memristor-based neural logic blocks for nonlinearly separable functions

IEEE Transactions on Computers

Volumn 62, Issue 8, 2013, Pages 1597-1606

  Soltiz, Michael ^a   Kudithipudi, Dhireesha ^a   Merkel, Cory ^a   Rose, Garrett S ^b   Pino, Robinson E ^c  

^a Kate Gleason College of Engineering   (United States)

^b AIR FORCE RESEARCH LABORATORY   (United States)

^c International   (United States)

Author keywords

memristors; neural networks; Neuromorphic; OCR; reconfigurable logic; stochastic gradient descent

Indexed keywords

ACTIVATION FUNCTIONS; BIOLOGICALLY INSPIRED; COMPLEX COMPUTATION; ENERGY DELAY PRODUCT; NEUROMORPHIC; OPTICAL CHARACTER RECOGNITION (OCR); RECONFIGURABLE LOGIC; STOCHASTIC GRADIENT DESCENT;

COMPLEX NETWORKS; DESIGN; MEMRISTORS; NETWORK LAYERS; NEURAL NETWORKS; OPTICAL CHARACTER RECOGNITION;

PASSIVE FILTERS;

EID: 84880141989     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2013.75     Document Type: Article

References (28)

1. C. Mead, "Neuromorphic Electronic Systems," Proc. IEEE, vol. 78, no. 10, pp. 1629-1636, Oct. 1990.
2. D.A. Drachman, "Do We Have Brain to Spare?" Neurology, vol. 64, no. 12, pp. 2056-2062, http://www.ncbi.nlm.nih.gov/pubmed/ 15985565, 2005.
3. G.S. Snider, "Spike-Timing-Dependent Learning in Memristive Nanodevices," Proc. IEEE Int'l Symp. Nanoscale Architectures, pp. 85-92, 2008.
4. C. Zamarren?o Ramos, L.A. Camun? as Mesa, J.A. Pe'rez-Carrasco, T. Masquelier, T. Serrano-Gotarredona, and B. Linares-Barranco, "On Spike-Timing-Dependent-Plasticity, Memristive Devices, and Building a Self-Learning Visual Cortex," Frontiers in Neuroscience, vol. 5, p. 26, 2011.
5. S.H. Jo, T. Chang, I. Ebong, B.B. Bhadviya, P. Mazumder, and W. Lu, "Nanoscale Memristor Device as Synapse in Neuromorphic Systems," Nano letters, vol. 10, no. 4, pp. 1297-301, http:// www.ncbi.nlm.nih.gov/pubmed/ 20192230, Apr. 2010.
6. D. Chabi, W. Zhao, D. Querlioz, and J.-o. Klein, "Robust Neural Logic Block (NLB) Based on Memristor Crossbar Array," Proc. IEEE/ACM Int'l Symp. Nanoscale Architectures (NANOARCH), pp. 137-143, 2011.
7. K.K. Likharev, "Neuromorphic CMOL Circuits," Nanotechnology, vol. 1, pp. 339-342, 2003.
8. H. Manem, J. Rajendran, and G.S. Rose, "Stochastic Gradient Descent Inspired Training Technique for a CMOS / Nano Memristive Trainable Threshold Gate Array," IEEE Trans. Circuits and Systems, vol. 59, no. 5, pp. 1051-1060, May 2012.
9. I. Ebong and P. Mazumder, "CMOS and Memristor-Based Neural Network Design for Position Detection," Proc. IEEE, vol. 100, no. 6, pp. 2050-2060, June 2012.
10. B.L. Mouttet, "Crossbar Control Circuit," Patent US 7 609 086, Oct. 2009.
11. B. Mouttet, "Proposal for Memristors in Signal Processing," Proc. Int'l Conf. Inst. of Computer Science Informatics and Telecomm. Eng. (Nano-Net), pp. 11-13, 2009.
12. E. Farquhar, C. Gordon, and P. Hasler, "A Field Programmable Neural Array," Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS '06), pp. 4117-4120, May 2006.
13. G. Scheler, "Memorization in a Neural Network with Adjustable Transfer Function and Conditional Gating," Quantitative Biology, vol. 1, 2004.
14. G. Scheler, "Regulation of Neuromodulator Receptor Efficacy - Implications for Whole-Neuron and Synaptic Plasticity," Progress in Neurobiology, vol. 72, no. 6, pp. 399-415, 2004. (Pubitemid 38728989)
15. G.S. Rose, R. Pino, and Q. Wu, "A Low-Power Memristive Neuromorphic Circuit Utilizing a Global/Local Training Mechanism," Proc. Int'l Joint Conf. Neural Networks (IJCNN), pp. 2080-2086, 2011.
16. T. Goh, P. Wang, and H. Lui, "Learning Algorithm for the Enhanced Fuzzy Perceptron," Proc. Int'l Joint Conf. Neural Networks (IJCNN), pp. 435-440, 1992.
17. D. Palmer-Brown and M. Kang, "ADFUNN : An Adaptive Function Neural Network," Proc. Seventh Int'l Conf. Adaptive and Natural Computing Algorithms (ICANNGA '05), 2005.
18. M. Sahami, "Learning Non-Linearly Separable Boolean Functions with Linear Threshold Unit Trees and Madaline-Style Networks," Proc. 11th Nat'l Conf. Artificial Intelligence, pp. 335-341, 1993.
19. W. Wang, T.T. Jing, and B. Butcher, "FPGA Based on Integration of Memristors and CMOS Devices," Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS), pp. 1963-1966, 2010.
20. M. Soltiz, C. Merkel, D. Kudithipudi, and G.S. Rose, "RRAMBased Adaptive Neural Logic Block for Implementing Non- Linearly Separable Functions in a Single Layer," Proc. IEEE/ ACM Int'l Symp. Nanoscale Architectures (NANOARCH '12), 2012.
21. D.B. Strukov, G.S. Snider, D.R. Stewart, and R.S. Williams, "The Missing Memristor Found," Nature, vol. 453, pp. 80-83, 2008. (Pubitemid 351630336)
22. T. Roska and L. Chua, "The CNN Universal Machine: An Analogic Array Computer," IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 40, no. 3, pp. 163-173, Mar. 1993. (Pubitemid 23700453)
23. M. Hansen, "Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering," IEEE Design & Test of Computers, vol. 16, no. 3, pp. 72-80, July 1999. (Pubitemid 30497933)
24. P. Chong Sis 1.3 Unofficial Distribution, http://embedded.eecs. berkeley.edu/Alumni/pchong/sis.html, 2013.
25. A. Rajavelu, M. Musavi, and M. Shirvaikar, "A Neural Network Approach to Character Recognition," Neural Networks, vol. 2, no. 5, pp. 387-393, 1989. (Pubitemid 20609011)
26. B. Hussain and M. Kabuka, "A Novel Feature Recognition Neural Network and Its Application to Character Recognition," IEEE Trans. Pattern Analysis and Machine Intelligence, vol. 16, no. 1, pp. 98-106, Jan. 1994.
27. O.D. Trier, A.K. Jain, and T. Taxt, "Feature Extraction Methods for Character Recognition- A Survey," Pattern Recognition, vol. 29, no. 4, pp. 641-662, 1996. (Pubitemid 126398335)
28. http://qnetv2k.com/Qnet2000Manual/html/qnet65ym.htm, 2013.