Stochastic gradient descent inspired training technique for a CMOS/nano memristive trainable threshold gate array

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 59, Issue 5, 2012, Pages 1051-1060

  Manem, Harika ^a   Rajendran, Jeyavijayan ^b   Rose, Garrett S ^c  

^a STATE UNIVERSITY OF NEW YORK   (United States)

^b POLYTECHNIC UNIVERSITY   (United States)

^c AIR FORCE RESEARCH LABORATORY   (United States)

Author keywords

Digital integrated circuits; machine learning; memristor; nanoelectronics; neural networks; VLSI

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATION THEORY; DIGITAL INTEGRATED CIRCUITS; GRADIENT METHODS; INTEGRATED CIRCUIT DESIGN; LEARNING ALGORITHMS; LEARNING SYSTEMS; MACHINE LEARNING; MEMRISTORS; NANOELECTRONICS; NEURAL NETWORKS; RESONANT TUNNELING; STOCHASTIC SYSTEMS; THRESHOLD ELEMENTS;

DESIGN AND IMPLEMENTATIONS; MEMRISTOR; NEUROMORPHIC COMPUTING; PERFORMANCE CHARACTERISTICS; STOCHASTIC GRADIENT DESCENT; TECHNOLOGY MIGRATION; TRAINING TECHNIQUES; VLSI;

COMPUTER CIRCUITS;

EID: 84860883459     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2012.2190665     Document Type: Article

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