Memristor bridge synapse-based neural network and its learning

IEEE Transactions on Neural Networks and Learning Systems

Volumn 23, Issue 9, 2012, Pages 1426-1435

  Adhikari, Shyam Prasad ^a   Yang, Changju ^a   Kim, Hyongsuk ^a   Chua, Leon O ^b  

^a Chonbuk National University   (South Korea)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Chip in the loop; memristor; memristor bridge synapse; neural network

Indexed keywords

ANALOG NEURAL NETWORK; CHIP-IN-THE-LOOP; HARDWARE ARCHITECTURE; LEARNING SCHEMES; MEMRISTOR; PROPOSED ARCHITECTURES; SPATIAL NONUNIFORMITY; SYNAPTIC WEIGHT;

HARDWARE; MEMRISTORS; MULTILAYER NEURAL NETWORKS; NETWORK ARCHITECTURE; NEURAL NETWORKS; NONVOLATILE STORAGE; PASSIVE FILTERS; RESISTORS;

COMPUTER HARDWARE;

ALGORITHM; ARTIFICIAL NEURAL NETWORK; BIOMIMETICS; COMPUTER AIDED DESIGN; DEVICE FAILURE ANALYSIS; DEVICES; EQUIPMENT DESIGN; IMPEDANCE; SIGNAL PROCESSING; SYNAPSE;

ALGORITHMS; BIOMIMETICS; COMPUTER-AIDED DESIGN; ELECTRIC IMPEDANCE; EQUIPMENT DESIGN; EQUIPMENT FAILURE ANALYSIS; NEURAL NETWORKS (COMPUTER); SIGNAL PROCESSING, COMPUTER-ASSISTED; SYNAPSES;

EID: 84876895659     PISSN: 2162237X     EISSN: 21622388     Source Type: Journal    
DOI: 10.1109/TNNLS.2012.2204770     Document Type: Article

References (33)

1. A. Waibal, T. Hanazawa, G. Hinton, K. Shikano, and K. J. Lang, "Phoneme recognition using time-delay neural networks," IEEE Trans. Acoust. Speech Signal Process., vol. 37, no. 3, pp. 328-339, Mar. 1989.
2. Y. LeCun, B. Boser, J. S. Denker, D. Henderson, R. E. Howard, W. Hubbard, and L. D. Jackel, "Back-propagation applied to handwritten zip code recognition," Neural Comput., vol. 1, no. 4, pp. 541-551, 1989.
3. H. Rowley, S. Baluja, and T. Kanade, "Neural network based face detection," IEEE Trans. Pattern Recognit. Mach. Intell., vol. 2, no. 1, pp. 23-38, Jan. 1998.
4. R. Fierro and F. L. Lewis, "Control of nonholonomic mobile robot using neural networks," IEEE Trans. Neural Netw., vol. 9, no. 4, pp. 589-600, Jul. 1998.
5. F. L. Lewis, A. Yegildirek, and K. Liu, "Multilayer neural net robot controller with guaranteed tracking performance," IEEE Trans. Neural Netw., vol. 7, no. 2, pp. 388-399, Mar. 1996.
6. J. B. Lont and W. Guggenbuhl, "Analog CMOS implementation of a multilayer perceptron with nonlinear synapses," IEEE Trans. Neural Netw., vol. 2, no. 3, pp. 457-465, May 1992.
7. M. Holler, S. Tam, H. Castro, and R. Benson, "An electrically trainable artificial neutral network (ETANN) with 102 040 floating gate synapses," in Proc. Neural Netw. Int. Joint Conf., 1989, pp. 191-196.
8. A. J. Montalvo, R. S. Gyuresik, and J. J. Paulos, "Toward a general purpose analog VLSI neural network with on-chip learning," IEEE Trans. Neural Netw., vol. 8, no. 2, pp. 413-423, Mar. 1997.
9. T. Shima, T. Kimura, Y. Kamatani, T. Itakura, Y. Fujita, and T. Iida, "Neuro chips with on-chip back-propagation and/or hebbian learning," IEEE J. Solid State Circuits, vol. 27, no. 12, pp. 1868-1876, Dec. 1992.
10. J. Misra and I. Saha, "Artificial neural networks in hardware: A survey of two decades of progress," Neurocomputing, vol. 74, nos. 1-3, pp. 239-255, 2010.
11. F. M. Diasa, A. Antunesa, and A. M. Motab, "Artificial neural networks: A review of commercial hardware," Eng. Appl. Artif. Intell., vol. 17, no. 8, pp. 945-952, 2004.
12. L. M. Reyneri, "Implementation issues of neuro-fuzzy hardware: Going toward HW/SW co-design," IEEE Trans. Neural Netw., vol. 14, no. 1, pp. 176-194, Jan. 2003.
13. D. Hammerstrom, "A survey of bio-inspired and other alternative architectures," in Nanotechnology: Information Technology-II, vol. 4, R. Waser, Ed. New York: Wiley-VCH Verlag, 2008, pp. 251-285.
14. P. D. Moerland and E. Fiesler, Neural Network Adaptations to Hardware Implementations, E. Fiesler and R. Beale Eds. London, U.K.: Oxford Univ. Press, 1997, pp. 1-13.
15. S. Draghici, "Neural networks in analog hardware-design and implementation issues," Int. J. Neural Syst., vol. 10, no. 3, pp. 19-42, 2000.
16. H. P. Graf, L. D. Jackel, R. E. Howard, B. Straughn, J. S. Denker, W. Hubbard, D. M. Tennant, and D. Schwartz, "VLSI implementation of a neural network memory with several hundreds of neurons," in Proc. AIP Conf. Neural Netw., 1987, pp. 182-187.
17. T. Morishita, Y. Tamura, T. Otsuki, and G. Kano, "A BiCMOS analog neural network with dynamically updated weights," IEICE Trans. Electron., vol. 75, no. 3, pp. 297-302, 1992.
18. M. Jabri and B. Flower, "Weight perturbation: An optimal architecture and learning technique for analog VLSI feedforward and recurrent multilayer networks," IEEE Trans. Neural Netw., vol. 3, no. 1, pp. 154-157, Jan. 1992.
19. Y. Maeda, H. Hirano, and Y. Kanata, "A learning rule of neural networks via simultaneous perturbation and its hardware implementation," Neural Netw., vol. 8, no. 2, pp. 251-259, 1995.
20. K. Hirotsu and M. A. Brooke, "An analog neural network chip with random weight change learning algorithm," in Proc. Int. Joint Conf. Neural Netw., 1993, pp. 3031-3034.
21. S. M. Tam, B. Gupta, H. A. Castro, and M. Holler, "Learning on analog VLSI network chip," in Proc. IEEE Int. Conf. Syst. Man Cybern., Nov. 1990, pp. 701-703.
22. B. Erkmen, N. Kahraman, R. A. Vural, and T. Yildirim, "Conic section function neural network circuitry for offline signature recognition," IEEE Trans. Neural Netw., vol. 21, no. 4, pp. 667-672, Apr. 2010.
23. L. O. Chua, "Memristor-the missing circuit element," IEEE Trans. Circuit Theory, vol. 18, no. 5, pp. 507-519, Sep. 1971.
24. D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, "The missing memristor found," Nature, vol. 453, no. 7191, pp. 80-83, 2008.
25. G. Snider, "Self-organized computation with unreliable memristive nanodevices," Nanotechnology, vol. 18, no. 36, pp. 1-13, 2007.
26. Y. Ho, G. M. Huang, and P. Li, "Dynamical properties and design analysis for nonvolatile memristor memories," IEEE Trans. Circuits Syst. I, vol. 58, no. 4, pp. 724-736, Apr. 2011.
27. S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder, and W. Lu, "Nanoscale memristor device as synapse in neuromorphic systems," Nano Lett., vol. 10, no. 4, pp. 1297-1301, 2010.
28. A. Afifi, A. Ayatollahi, and F. Raissi, "Implementation of biologically plausible spiking neural network models on the memristor crossbarbased CMOS/nano circuits," in Proc. Eur. Conf. Circuit Theory Design, 2009, pp. 563-566.
29. K. D. Cantley, A. Subramaniam, H. J. Stiegler, R. A. Chapman, and E. M. Vogel, "Neural learning circuits utilizing nano-crystalline silicon transistors and memristors," IEEE Trans. Neural Netw. Learn. Syst., vol. 23, no. 4, pp. 565-573, Apr. 2012.
30. H. Kim, M. P. Sah, C. Yang, T. Roska, and L. O. Chua, "Memristor bridge synapse," Proc. IEEE, vol. 100, no. 6, pp. 2061-2070, Jun. 2012.
31. H. Kim, M. P. Sah, C. Yang, T. Roska, and L. O. Chua, "Neural synaptic weighting with a pulse-based memristor circuit," IEEE Trans. Circuit Syst. I, vol. 59, no. 1, pp. 148-158, Jan. 2012.
32. Y. Joglekar and S. Wolf, "The elusive memristor: Properties of basic electrical circuits," Eur. J. Phys., vol. 30, no. 4, pp. 661-675, 2009.
33. T. Fawcett, ROC Graphs: Notes and Practical Considerations for Researchers. Boston, MA: Kluwer, 2004.