Dynamic cache pooling in 3D multicore processors

ACM Journal on Emerging Technologies in Computing Systems

Volumn 12, Issue 2, 2015, Pages

  Zhang, Tiansheng ^a   Meng, Jie ^a   Coskun, Ayse K ^a  

^a Boston University   (United States)

Author keywords

3D stacking; Cache resource pooling; Energy efficiency; Policy; Runtime policy

Indexed keywords

PUBLIC POLICY; SOFTWARE ARCHITECTURE; THREE DIMENSIONAL INTEGRATED CIRCUITS;

3D STACKING; ARCHITECTURAL COMPONENTS; INTERCONNECT LATENCY; MULTI-CORE PROCESSOR; MULTICORE ARCHITECTURES; PROPOSED ARCHITECTURES; RESOURCE POOLING; RUNTIMES;

ENERGY EFFICIENCY;

EID: 84941196114     PISSN: 15504832     EISSN: 15504840     Source Type: Journal    
DOI: 10.1145/2700247     Document Type: Article

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