Dynamic thermal management in 3D multi-core architecture through run-time adaptation

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2011, Pages 299-304

  Hameed, Fazal ^a   Al Faruque, Mohammad Abdullah ^a   Henkel, Jörg ^a  

^a KARLSRUHE INSTITUTE OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

3D PROCESSORS; CORE LEVELS; DIVERSE APPLICATIONS; DYNAMIC THERMAL MANAGEMENT; DYNAMIC VOLTAGE AND FREQUENCY SCALING; HOTSPOTS; MULTICORE ARCHITECTURES; POWER DENSITIES; REDUCED POWER CONSUMPTION; RUNTIME ADAPTATION; THERMAL BEHAVIORS; THERMAL MANAGEMENT; TRANSISTOR DENSITY; WIRE LENGTH;

ARCHITECTURE; COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; INDUSTRIAL MANAGEMENT; THREE DIMENSIONAL;

TEMPERATURE CONTROL;

EID: 79957556743     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)

1. International Technology Roadmap for Semiconductors, http://www.itrs.net.
2. P. Chaparro, J. Gonzalez, G. Magklis, Q. Cai and A. Gonzalez, "Understanding the Thermal Implications of Multicore Architectures", IEEE Transaction on Parallel and Distributed Systems, vol. 18, No. 8, pp. 1055-1065, August, 2007.
3. R. Jayaseelan and T. Mitra, "A Hybrid Local-Global Approach for Multi-core Thermal Management", ICCAD'09: International Conference on Computer Aided Design, pp. 314-320, 2009.
4. D. Brooks and M. Martonosi, "Dynamic Thermal Management for High-Performance Microprocessors", HPCA'01: International Symposium on High-Performance Computer Architecture, pp. 171-182, 2001.
5. J. Donald and M.Martonosi, "Techniques for Multi-core Thermal Managment: Classification and New Exploration", ISCA'06: International Symposium on Computer Architecture, pp. 78-88, 2006.
6. K. Skadron, M. R. Stan, K. Sankaranarayanan, W. Huang,S. Velusamy, and D. Tarjan, "Temperature-aware microarchitecture: Modeling and implementation", ACM Transactions on Architecture and Code Optimization, vol. 1, No. 1, pp. 94-125, 2004.
7. R. I. Bahar and S. Manne, "Power and Energy Reduction via Pipeline Balancing", ISCA'01: International Symposium on Computer Architecture, pp. 218-229, 2001.
8. G. M. Link and N. Vijaykrishnan, "Thermal Trends in Emerging Technologies", ISQED'06: International Symposium on Quality Electronic Design, pp. 625-632, 2006.
9. C. Zhu, Z. Gu, L. Shang, R.P. Dick and R.Joseph, "Three- Dimensional Chip-Multiprocessor Run-Time Thermal Management", IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems. vol. 27, No. 8, pp. 1479-1492, 2008.
10. K.Puttaswamy and Gabriel.H. Loh, " Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High performance 3D-Integrated Processor", HPCA'07: International Symposium on High-Performance Computer Architecture, pp. 193-204, 2007.
11. Gabriel H. Loh, "Extending the Effectivenes of 3D -Stacked DRAM Caches with an Adaptive Multi-Queue Policy", MICRO'09: International Symposium on Microarchitecture , pp. 201-212, 2009.
12. S. Thoziyoor, J. Ho Ahn, A. Monchiero, J. B. Brockman and N. P. Jouppi, "A Comprehensive Memory Modeling Tool and its Application to the Design and Analysis of Future Memory Hierarchies", ISCA08: International Symposium on Computer Architecture, pp. 51-62 , 2008.
13. Compaq Computer Corporation. Alpha 21264 Microprocessor Hardware Reference Manual, 1999.
14. K. Puttaswamy and G. Loh, "Implementing Register Files for High- Performance Microprocessors in a Die-Stacked (3D) Technology", ISVLSI' 06: International Symposium on VLSI, pp. 384-389, 2006.
15. D. Ernst, T. Austin, "Efficient dynamic scheduling through tag elimination", ISCA'02: International Symposium on Computer Architecture, pp. 37-46, 2002.
16. K. Puttaswamy and G. Loh. "Dynamic Instruction Schedulers in a 3- Dimensional Integration Technology", GLSVLSI'06: ACM/IEEE Great Lakes Symposium on VLSI, pp. 153-158, 2006.
17. G. H. Loh, "A Modular 3D Processor for Flexible Product Design and Technology Migration", Proceedings of the 5th ACM conference on Computing Frontiers, pp. 159-170, 2008.
18. D.H. Albonesi et al., "Dynamically Tuning Processor Resources with Adaptive Processing", IEEE Computer Society, vol 36, Issue 12, pp. 49-58,2003.
19. Sheng Li et al., "McPat: An Integrated Power, Area and Timing Modeling Framework for Multicore and Manycore Architectures", MICRO'09: International Symposium on Microarchitecture, pp. 469-480, 2009.
20. R. Desikan, D. Burger, and S.W. Keckler, " Measuring Experimental Error in Microprocessor Simulation", ISCA'01: International Symposium on Computer Architecture, pp. 266-277, 2001.
21. Y. Xie, G. H. Loh, B. Black, K. Bernstein, "Design Space Exploration for 3D Architectures", ACM Journal on Emerging Technologies in Computing Systems, vol. 2, No.2, pp. 65-103, 2006.