Design and management of 3D-stacked NUCA cache for chip multiprocessors

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2011, Pages 91-96

  Jung, Jongpil ^a   Kang, Kyungsu ^a   Kyung, Chong Min ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

3D IC; Cache partitioning; Energy; L2 cache; Performance

Indexed keywords

3D IC; CACHE PARTITIONING; ENERGY; L2 CACHE; PERFORMANCE;

CACHE MEMORY; ENERGY UTILIZATION; LAKES; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; SYSTEMS ANALYSIS; THREE DIMENSIONAL; VLSI CIRCUITS;

DESIGN;

EID: 79957785400     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1973009.1973028     Document Type: Conference Paper

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