Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors

SIGMETRICS/Performance'09 - Proceedings of the 11th International Joint Conference on Measurement and Modeling of Computer Systems

Volumn 37, Issue 1, 2009, Pages 169-180

  Coskun, Ayse K ^a   Strong, Richard ^a   Tullsen, Dean M ^a   Rosing, Tajana Simunic ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

C.4 performance of systems : Modeling techniques; Reliability

Indexed keywords

CHIP MULTIPROCESSOR; DYNAMIC SCHEDULING; JOB SCHEDULING; MODELING TECHNIQUE; MULTICORE ARCHITECTURES; PEAK TEMPERATURES; PERFORMANCE OF SYSTEMS; POWER MANAGEMENTS; SIMULATION FRAMEWORK; TEMPERATURE-INDUCED; THERMAL CYCLE; THERMAL HOT SPOTS; THERMAL INTERACTION; THERMAL MANAGEMENT;

ELECTRIC POWER MEASUREMENT; ENERGY MANAGEMENT; MULTIPROCESSING SYSTEMS; RELIABILITY; SOFTWARE ARCHITECTURE;

SCHEDULING;

EID: 70349732333     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1555349.1555369     Document Type: Conference Paper

References (35)

1. M. V. Biesbrouck, T. Sherwood, and B. Calder. A co-phase matrix to guide simultaneous multithreading simulation. In International Symposium on Performance Analysis of Systems and Software, pages 45-56, 2004.
2. N. L. Binkert, E. G. Hallnor, and S. K. Reinhardt. Network-oriented full-system simulation using M5. In Computer Architecture Evaluation using Commercial Workloads (CAECW), 2003.
3. P. Bose. Power-efficient microarchitectural choices at the early design stage. In Keynote Address, Workshop on Power-Aware Computer Systems, 2003.
4. D. Brooks and M. Martonosi. Dynamic thermal management for high-performance microprocessors. In High-Performance Computer Architecture (HPCA), pages 171-182, 2001.
5. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: a framework for architectural-level power analysis and optimizations. In International Symposium on Computer architecture, pages 83-94, 2000.
6. D. C. Burger and T. M. Austin. The simplescalar tool set, version 2.0. Technical Report CS-TR-97-1342, University of Wisconsin, Madison, June 1997.
7. J. Chang and G. S. Sohi. Cooperative cache partitioning for chip multiprocessors. In ACM International Conference on Supercomputing, pages 242.252, 2007.
8. A. K. Coskun, T. Rosing, and K. Whisnant. Temperature aware task scheduling in MPSoCs. In Design Autom. and Test in Europe (DATE), pages 1659.1664, 2007.
9. G. Dhiman and T. Rosing. Dynamic voltage frequency scaling for multi-tasking systems using online learning. In International Symposium on Low Power Electronic Design (ISLPED), pages 207-212, 2007.
10. J. Donald and M. Martonosi. Leveraging simultaneous multithreading for adaptive thermal control. In Second Workshop on Temperature-Aware Computer Systems, 2005.
11. J. Donald and M. Martonosi. Techniques for multicore thermal management: Classification and new exploration. In International Symposium on Computer Architecture (ISCA), pages 78-88, 2006.
12. M. Gomaa, M. D. Powell, and T. N. Vijaykumar. Heat-and-Run: leveraging SMT and CMP to manage power density through the operating system. In Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 260-270, 2004.
13. S. Gunther, F. Binns, D. M. Carmean, and J. C. Hall. Managing the impact of increasing microprocessor power consumption. In Intel Technology Journal, 2001.
14. S. Heo, K. Barr, and K. Asanovic. Reducing power density through activity migration. In ISLPED, pages 217.222, 2003.
15. Intel pentium 4 processor in the 423-pin package thermal design guidelines. Technical Report 249203-001, Intel, November 2000.
16. R. Iyer et al. QoS policies and architecture for cache/memory in CMP platforms. In ACM Sigmetrics, pages 25-36, 2007.
17. Failure mechanisms and models for semiconductor devices, JEDEC publication JEP122C. http://www.jedec.org.
18. A. Karlin, M. Manesse, L. McGeoch, and S. Owicki. Competitive randomized algorithms for nonuniform problems. In Algorithmica, pages 542.571, 1994.
19. A. Kumar, L. Shang, L.-S. Peh, and N. K. Jha. HybDTM: a coordinated hardware-software approach for dynamic thermal management. In Design Automation Conference (DAC), pages 548-553, 2006.
20. R. Kumar, D. M. Tullsen, and N. P. Jouppi. Core architecture optimization for heterogeneous chip multiprocessors. In Parallel Architectures and Compilation Techniques (PACT), pages 23-32, 2006.
21. R. Kumar, V. Zyuban, and D. M. Tullsen. Interconnections in multi-core architectures: Understanding mechanisms, overheads and scaling. In ISCA, pages 408-419, 2005.
22. S. Murali et al. Temperature control of high-performance multicore platforms using convex optimization. In Design Autom. and Test in Europe (DATE), pages 110-115, 2008.
23. H. Nguyen. Multilevel interconnect reliability on the effects of electro-thermomechanical stresses. Ph.D. dissertation, University of Twente, Netherlands, 2004.
24. M. Powell, E. Schuchman, and T. Vijaykumar. Balancing resource utilization to mitigate power density in processor pipelines. In International Symposium on Microarchitecture, pages 294-304, 2005.
25. T. S. Rosing, K. Mihic, and G. D. Micheli. Power and reliability management of SoCs. In IEEE Transactions on VLSI, 15(4), pages 391-403, April 2007.
26. T. Sherwood, G. H. E. Perelman, and B. Calder. Automatically characterizing large scale program behavior. In ASPLOS, 2002.
27. K. Skadron. Hybrid architectural dynamic thermal management. In Design Autom. and Test in Europe (DATE), pages 10-15, 2004.
28. K. Skadron, M. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. Temperature-aware microarchitecture. In ISCA, pages 2-13, 2003.
29. J. Smith. Characterizing computer performance with a single number. In Communication of ACM, 31(10), pages 1202-1206, 1988.
30. J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers. The case for lifetime reliability-aware microprocessors. In ISCA, pages 276-287, 2004.
31. J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers. The impact of technology scaling on lifetime reliability. In International Conference on Dependable Systems and Networks (DSN), pages 177-186, 2004.
32. J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers. Lifetime reliability: Toward an architectural solution. In IEEE Micro, 25(3):70-80, 2005.
33. H. Su, F. Liu, A. Devgan, E. Acar, and S. Nassif. Full-chip leakage estimation considering power supply and temperature variations. In ISLPED, pages 78-83, 2003.
34. D. Tarjan, S. Thoziyoor, and N. P. Jouppi. CACTI 4.0. Technical Report HPL-2006-86, HP Laboratories Palo Alto, 2006.
35. Q. Wu, M. Martonosi, D. W. Clark, V. J. Reddi, D. Connors, Y. Wu, J. Lee, and D. Brooks. A dynamic compilation framework for controlling microprocessor energy and performance. In International Symposium on Microarchitecture, pages 271-282, 2005.