Dynamic cache pooling for improving energy efficiency in 3D stacked multicore processors

IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC

Volumn , Issue , 2013, Pages 210-215

  Meng, Jie ^a   Zhang, Tiansheng ^a   Coskun, Ayse K ^a  

^a Boston University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY EFFICIENCY; MULTIPROCESSING SYSTEMS; PROGRAMMABLE LOGIC CONTROLLERS; SOFTWARE ARCHITECTURE;

ARCHITECTURAL COMPONENTS; ENERGY DELAY PRODUCT; INTERCONNECT LATENCY; MULTI-CORE PROCESSOR; MULTICORE ARCHITECTURES; RESOURCE POOLING; STACKED SYSTEMS; TOTAL CHIP AREA;

THREE DIMENSIONAL;

EID: 84899500043     PISSN: 23248432     EISSN: 23248440     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI-SoC.2013.6673277     Document Type: Conference Paper

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