Application-to-core mapping policies to reduce memory interference in multi-core systems

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2012, Pages 455-456

  Das, Reetuparna ^a   Ausavarungnirun, Rachata ^b   Mutlu, Onur ^b   Kumar, Akhilesh ^c   Azimi, Mani ^c  

^a UNIVERSITY OF MICHIGAN   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

Interconnect; Memory; Multicore; Scheduling

Indexed keywords

INTERCONNECT; INTERCONNECT POWER; MANY-CORE; MEMORY CONTROLLER; MULTI CORE; MULTI-CORE SYSTEMS; ON-CHIP NETWORKS; SHARED RESOURCES; SYSTEM THROUGHPUT;

DATA STORAGE EQUIPMENT; MICROPROCESSOR CHIPS; PARALLEL ARCHITECTURES; SCHEDULING;

INTERFERENCE SUPPRESSION;

EID: 84867488506     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2370816.2370893     Document Type: Conference Paper

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