A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 108-109

  Howard, Jason ^a   Dighe, Saurabh ^a   Hoskote, Yatin ^a   Vangal, Sriram ^a   Finan, David ^a   Ruhl, Gregory ^a   Jenkins, David ^a   Wilson, Howard ^a   Borkar, Nitin ^a   Schrom, Gerhard ^a   Pailet, Fabrice ^a   Jain, Shailendra ^b   Jacob, Tiju ^b   Yada, Satish ^b   Marella, Sraven ^b   Salihundam, Praveen ^b   Erraguntla, Vasantha ^b   Konow, Michael ^a   Riepen, Michael ^a   Droege, Guido ^a   Lindemann, Joerg ^a   Gries, Matthias ^a   Apel, Thomas ^a   Henriss, Kersten ^a   Lund Larsen, Tor ^a   Steibl, Sebastian ^a   Borkar, Shekhar ^a   De, Vivek ^a   Van Der Wijngaart, Rob ^a   Mattson, Timothy ^a   more..

^a INTEL CORPORATION   (United States)

^b INTEL TECHNOLOGY INDIA PVT LTD   (India)

Author keywords

[No Author keywords available]

Indexed keywords

BIDIRECTIONAL SYSTEM; DIE AREA; FREQUENCY-SCALING; HIGH-SPEED; I/O BANDWIDTH; L2 CACHE; MEMORY ACCESS; MEMORY BANDWIDTHS; MESH NETWORK; METAL-GATE; MICROPROCESSOR DESIGNS; PENTIUM; POWER SAVINGS; PROCESSOR PERFORMANCE; PROGRAMMING MODELS; PROTOTYPE CHIP; SHARED MEMORIES;

CMOS INTEGRATED CIRCUITS; DIES; ELECTRIC POTENTIAL; ENERGY EFFICIENCY; MICROPROCESSOR CHIPS; NANOTECHNOLOGY;

MESSAGE PASSING;

EID: 77952123736     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5434077     Document Type: Conference Paper

References (5)

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2. K. Mistry, C. Allen, C. Auth, et al., "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging", IEDM Dig. Tech. Papers, Dec. 2007.
3. S. Vangal, J. Howard, G. Ruhl, et al., "An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS", ISSCC Dig. Tech. Papers, pp. 98-99, Feb., 2007.
4. L. Smith and M. Bull, "Development of hybrid mode MPI/OpenMP applications", Scientific Programming, Vol. 9, No 2-3, 83-98, 2001.
5. R. Kumar, G. Hinton, "A Family of 45nm IA Processors", ISSCC Dig. Tech. Papers, pp. 58-59, Feb., 2009.