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Volumn 30, Issue 8, 2009, Pages 846-848

A new investigation of data retention time in truly nanoscaled DRAMs

Author keywords

Data retention time; DRAM; Gate induced drain leakage (GIDL) currents; Recess channel array transistor (RCAT); Trap assisted tunneling (TAT)

Indexed keywords

DATA RETENTION TIME; DRAM; GATE-INDUCED DRAIN LEAKAGE (GIDL) CURRENTS; RECESS CHANNEL ARRAY TRANSISTOR (RCAT); TRAP-ASSISTED TUNNELING (TAT);

EID: 68249161195     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2009.2023248     Document Type: Article
Times cited : (143)

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  • 3
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    • New model of gate-induced drain current density in an NMOS transistor
    • Nov
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    • Prediction of data retention time distribution of DRAM by physics-based statistical simulation
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    • S. Jin, J.-H. Yi, J. H. Choi, D. G. Kang, Y. J. Park, and H. S. Min, "Prediction of data retention time distribution of DRAM by physics-based statistical simulation," IEEE Trans. Electron Devices vol. 52, no. 11, pp. 2422-2427, Nov. 2005.
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    • Jin, S.1    Yi, J.-H.2    Choi, J.H.3    Kang, D.G.4    Park, Y.J.5    Min, H.S.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.