Base-delta-immediate compression: Practical data compression for on-chip caches

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2012, Pages 377-388

  Pekhimenko, Gennady ^a   Seshadri, Vivek ^a   Mutlu, Onur ^a   Kozuch, Michael A ^b   Gibbons, Phillip B ^b   Mowry, Todd C ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Cache compression; Caching; Memory

Indexed keywords

BANDWIDTH USAGE; BASELINE SYSTEMS; CACHE ACCESS; CACHE CAPACITY; CACHE SIZE; CACHING; COMPRESSION ALGORITHMS; COMPRESSION APPROACH; COMPRESSION TECHNIQUES; DATA PATTERNS; HARDWARE COMPLEXITY; LOW DYNAMIC RANGE; MINIMAL EFFECTS; MULTI CORE; OFF-CHIP; ON CHIPS; ON-CHIP CACHE; PERFORMANCE BENEFITS;

ALGORITHMS; BANDWIDTH COMPRESSION; CACHE MEMORY; DATA STORAGE EQUIPMENT; HARDWARE; PARALLEL ARCHITECTURES;

DATA COMPRESSION;

EID: 84867500642     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2370816.2370870     Document Type: Conference Paper

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