Device Optimization for Ultra-Low Power Digital Sub-Threshold Operation

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2004-January, Issue January, 2004, Pages 96-101

  Paul, Bipul C ^a   Raychowdhury, Arijit ^a   Roy, Kaushik ^a  

^a Purdue University   (United States)

Author keywords

Device optimization; sub threshold operation; ultra low power applications

Indexed keywords

CMOS INTEGRATED CIRCUITS; DESIGN; LOGIC CIRCUITS; LOGIC DESIGN; POWER ELECTRONICS; THRESHOLD LOGIC; THRESHOLD VOLTAGE;

DEVICE OPTIMIZATION; DIGITAL SUB-THRESHOLD OPERATIONS; ORDERS OF MAGNITUDE; POWER DELAY PRODUCT; SUB-THRESHOLD REGIONS; SUBTHRESHOLD OPERATION; ULTRA HIGH PERFORMANCE; ULTRALOW POWER APPLICATION;

LOW POWER ELECTRONICS;

EID: 84932157628     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2004.240809     Document Type: Conference Paper

References (18)

1. C. H. Choi, K. Nam, Z Yu, and R. W Dutton, "Impact of Gate Tunneling Current in Scaled MOS on Circuit Performance: A Simulation Study," in IEEE Trans. on Electron Devices, Vol. 48, No. 12, pp. 2823-2829, 2001.
2. H. S. Momose, M. Ono, T. Yoshitomo, T. Ohguro, S. Nakamura, M. Saito, and H. Iwai, "1.5 nm Direct-Tunneling Gate Oxide Si MOS-FET's," in IEEE Trans. Electron Devices, Vol. 43, pp. 1233-1242, Aug. 1996.
3. J. Jomaah, G. Ghibaudo, and F. Balestra, "Band-to-Band Tunneling Model of Gate Induced Drain Leakage Current in Silicon MOS Transistors," in Electronics Letters, Vol. 32, No. 8, pp. 767-769, 1996.
4. C. Chen and M. Sarrafzadeh, "Simultaneous Voltage Scaling and Gate Sizing for Low-power Design," in Proc. of IEEE Trans. On Circuits and Systems II: Analog and Digital Signal, Vol. 49, pp. 400-408, June 2002.
5. C. H. Kim, and K. Roy, "Dynamic VTH scaling scheme for active leakage power reduction," in Proc. of Design, Automation and Test in Europe Conference and Exhibition, pp.163-167, 2002.
6. A. Agarwal, H. Li, and K. Roy, "A Single Vt Low-Leakage Gated- Ground Cache for Deep Submicron," in IEEE Journal of SolidState Circuits vol. 38, pp. 319-328, 2003.
7. G. Palumbo, F. Pappalardo, and S. Sannella, "Evaluation on Power Reduction Applying Gated Clock Approaches," in IEEE Intl. Symp. on Circuits and Systems, pp. 85-88, Vol. 4, 2002.
8. Y. Cao, C. Hu, X. Huang, A. B. Kahng, S. Muddu, D. Stroobandt and D. Sylvester, "Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design," in IEEE/ACM Intl. Conference on Computer Aided Design, ICCAD- 2000, pp. 56-61.
9. S. Katkoori, and S. Alupoaei, "RT-level Interconnect Optimization in DSM Regime," in Proc. of VLSI, pp. 143-148, 2000.
10. L. Entrena, C. Lopez, E. Olias, E. S. Millan, and J. A. Espejo, "Logic Optimization of Unidirectional Circuits with Structural Methods," in Proc. of On-line Testing Workshop, pp. 43-47, 2001.
11. E. S. Millan, L. Entrena, and J. A. Espejo, "On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization," in Proc. of Digital Systems Design, pp. 292-299, 2001.
12. H. Soeleman, K. Roy, and B. C. Paul, "Robust Sub-threshold Logic for Ultra-Low Power Operation," in IEEE Trans. On VLSI Systems, Vol. 9, No. 1, pp. 90-99, 2001.
13. H. Soeleman, K. Roy, and B. C. Paul, "Robust Ultra-Low Power Sub-threshold DTMOS Logic," in IEEE Intl. Symp. On Low Power Electronics (ISLPED), pp. 94-96, 2000.
14. Y. Taur, and T. H. Ning, "Fundamentals of Modern VLSI Devices," Cambridge University Press, New York, 1998.
15. http://www-mtl.mit.edu/Well
16. Z. Lee, M.B. McIlrath, D.A. Antoniadis, "Two-dimensional doping profile characterization of MOSFET's by inverse modeling using characteristics in the subthreshold Region", IEEE Trans. on Elec. Dev., Aug. 1999, pp. 1640-1649.
17. X. Zhou, K. Y. Lim, and D. Lim., "A general approach to compact threshold voltage formulation based on 2-D numerical simulation and experimental correlation for deepsubmicron ULSI technology development" , IEEE Trans. On Elec. Dev., vol 47, Jan. 2000, pp. 214-221.
18. S. Odanaka, T. Yabu, N. Shimizu, H. Umimoto, and T. Ohzone, "A Self-Aligned Retrograde Twin-Well Structure with Burid P+-Layer," in IEEE Trans. On Elec. Dev., vol. 37, no. 7, pp. 1735-1742, 1990.