-
1
-
-
10844253861
-
'Recurrently connected silicon neurons with active dendrites for one-shot learning'
-
(IEEE Cat. No.04CH37541) (IEEE) (Vancouver, BC). doi: 10.1109/IJCNN.2004.1380858.
-
Arthur, J. V., and Boahen, K. (2004). "Recurrently connected silicon neurons with active dendrites for one-shot learning," in 2004 IEEE International Joint Conference on Neural Networks (IEEE Cat. No.04CH37541) (IEEE) (Vancouver, BC), 1699-1704. doi: 10.1109/IJCNN.2004.1380858.
-
(2004)
2004 IEEE International Joint Conference on Neural Networks
, pp. 1699-1704
-
-
Arthur, J.V.1
Boahen, K.2
-
2
-
-
77957556785
-
Neural dynamics in reconfigurable silicon
-
doi: 10.1109/TBCAS.2010.2055157
-
Basu, A., Ramakrishnan, S., Petre, C., Koziol, S., Brink, S., and Hasler, P. E. (2010). Neural dynamics in reconfigurable silicon. IEEE Trans. Biomed. Circuits Syst. 4, 311-319. doi: 10.1109/TBCAS.2010.2055157.
-
(2010)
IEEE Trans. Biomed. Circuits Syst
, vol.4
, pp. 311-319
-
-
Basu, A.1
Ramakrishnan, S.2
Petre, C.3
Koziol, S.4
Brink, S.5
Hasler, P.E.6
-
3
-
-
0033740171
-
Point-to-point connectivity between neuromorphic chips using address events
-
doi: 10.1109/82.842110
-
Boahen, K. (2000). Point-to-point connectivity between neuromorphic chips using address events. IEEE Trans. Circuits Syst. II Analog Digit. Signal Process. 47, 416-434. doi: 10.1109/82.842110.
-
(2000)
IEEE Trans. Circuits Syst. II Analog Digit. Signal Process
, vol.47
, pp. 416-434
-
-
Boahen, K.1
-
4
-
-
84875055083
-
A learning-enabled neuron array IC based upon transistor channel models of biological phenomena
-
doi: 10.1109/TBCAS.2012.2197858
-
Brink, S., Nease, S., Hasler, P., Ramakrishnan, S., Wunderlich, R., Basu, A., et al. (2013). A learning-enabled neuron array IC based upon transistor channel models of biological phenomena. IEEE Trans. Biomed. Circuits Syst. 7, 71-81. doi: 10.1109/TBCAS.2012.2197858.
-
(2013)
IEEE Trans. Biomed. Circuits Syst
, vol.7
, pp. 71-81
-
-
Brink, S.1
Nease, S.2
Hasler, P.3
Ramakrishnan, S.4
Wunderlich, R.5
Basu, A.6
-
6
-
-
84875118588
-
A simple programmable axonal delay scheme for spiking neural networks
-
doi: 10.1016/j.neucom.2012.12.004
-
Dowrick, T., Hall, S., and McDaid, L. (2013). A simple programmable axonal delay scheme for spiking neural networks. Neurocomputing 108, 79-83. doi: 10.1016/j.neucom.2012.12.004.
-
(2013)
Neurocomputing
, vol.108
, pp. 79-83
-
-
Dowrick, T.1
Hall, S.2
McDaid, L.3
-
7
-
-
44649101666
-
Cortical models onto CMOL and CMOS-architectures and performance/price
-
doi: 10.1109/TCSI.2007.907830
-
Gao, C., and Hammerstrom, D. (2007). Cortical models onto CMOL and CMOS-architectures and performance/price. IEEE Trans. Circuits Syst. I Regul. Pap. 54, 2502-2515. doi: 10.1109/TCSI.2007.907830.
-
(2007)
IEEE Trans. Circuits Syst. I Regul. Pap
, vol.54
, pp. 2502-2515
-
-
Gao, C.1
Hammerstrom, D.2
-
8
-
-
0029821128
-
A neuronal learning rule for sub-millisecond temporal coding
-
doi: 10.1038/383076a0
-
Gerstner, W., Kempter, R., van Hemmen, J. L., and Wagner, H. (1996). A neuronal learning rule for sub-millisecond temporal coding. Nature 383, 76-81. doi: 10.1038/383076a0.
-
(1996)
Nature
, vol.383
, pp. 76-81
-
-
Gerstner, W.1
Kempter, R.2
van Hemmen, J.L.3
Wagner, H.4
-
9
-
-
0034762808
-
Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons
-
doi: 10.1016/S0893-6080(01)00057-0
-
Goldberg, D., Cauwenberghs, G., and Andreou, A. (2001). Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons. Neural Netw. 14, 781-793. doi: 10.1016/S0893-6080(01)00057-0.
-
(2001)
Neural Netw
, vol.14
, pp. 781-793
-
-
Goldberg, D.1
Cauwenberghs, G.2
Andreou, A.3
-
10
-
-
54949132181
-
'Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks'
-
doi: 10.1109/FPL.2008.4629989.
-
Harkin, J., Morgan, F., Hall, S., Dudek, P., Dowrick, T., and McDaid, L. (2008). "Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks," in 2008 International Conference on Field Programmable Logic and Applications (IEEE) (Heidelberg), 483-486. doi: 10.1109/FPL.2008.4629989.
-
(2008)
2008 International Conference on Field Programmable Logic and Applications (IEEE) (Heidelberg)
, pp. 483-486
-
-
Harkin, J.1
Morgan, F.2
Hall, S.3
Dudek, P.4
Dowrick, T.5
McDaid, L.6
-
11
-
-
78049413105
-
A reconfigurable and biologically inspired paradigm for computation using network-on-chip and spiking neural networks
-
doi: 10.1155/2009/908740
-
Harkin, J., Morgan, F., McDaid, L., Hall, S., McGinley, B., and Cawley, S. (2009). A reconfigurable and biologically inspired paradigm for computation using network-on-chip and spiking neural networks. Int. J. Reconfig. Comput. 2009, 1-13. doi: 10.1155/2009/908740.
-
(2009)
Int. J. Reconfig. Comput
, vol.2009
, pp. 1-13
-
-
Harkin, J.1
Morgan, F.2
McDaid, L.3
Hall, S.4
McGinley, B.5
Cawley, S.6
-
12
-
-
84887424523
-
Finding a roadmap to achieve large neuromorphic hardware systems
-
doi: 10.3389/fnins.2013.00118
-
Hasler, J., and Marr, B. (2013). Finding a roadmap to achieve large neuromorphic hardware systems. Front. Neurosci. 7:118. doi: 10.3389/fnins.2013.00118.
-
(2013)
Front. Neurosci
, vol.7
, pp. 118
-
-
Hasler, J.1
Marr, B.2
-
13
-
-
0025659696
-
Active analog memories for neuro-computing
-
doi: 10.1109/ISCAS.1990.112638
-
Horio, Y., Ymamamoto, M., and Nakamura, S. (1990). Active analog memories for neuro-computing. IEEE Int. Symp. Circuits Syst. 4, 2986-2989. doi: 10.1109/ISCAS.1990.112638.
-
(1990)
IEEE Int. Symp. Circuits Syst
, vol.4
, pp. 2986-2989
-
-
Horio, Y.1
Ymamamoto, M.2
Nakamura, S.3
-
14
-
-
84898027442
-
Delay learning architectures for memory and classification
-
(in press)
-
Hussain, S., Basu, A., Wang, R., and Hamilton, T. (in press). Delay learning architectures for memory and classification. Neurocomputing 1-27.
-
Neurocomputing
, pp. 1-27
-
-
Hussain, S.1
Basu, A.2
Wang, R.3
Hamilton, T.4
-
15
-
-
84874185723
-
'DELTRON: neuromorphic architectures for delay based learning'
-
doi: 10.1109/APCCAS.2012.6419032.
-
Hussain, S., Basu, A., Wang, M., and Hamilton, T. J. (2012). "DELTRON: neuromorphic architectures for delay based learning," in 2012 IEEE Asia Pacific Conference on Circuits and Systems (IEEE) (Kaohsiung), 304-307. doi: 10.1109/APCCAS.2012.6419032.
-
(2012)
2012 IEEE Asia Pacific Conference on Circuits and Systems (IEEE) (Kaohsiung)
, pp. 304-307
-
-
Hussain, S.1
Basu, A.2
Wang, M.3
Hamilton, T.J.4
-
16
-
-
0742268989
-
Simple model of spiking neurons
-
doi: 10.1109/TNN.2003.820440
-
Izhikevich, E. M. (2003). Simple model of spiking neurons. IEEE Trans. Neural Netw. 14, 1569-1572. doi: 10.1109/TNN.2003.820440.
-
(2003)
IEEE Trans. Neural Netw
, vol.14
, pp. 1569-1572
-
-
Izhikevich, E.M.1
-
17
-
-
33644898137
-
Polychronization: computation with spikes
-
doi: 10.1162/089976606775093882
-
Izhikevich, E. M. (2006). Polychronization: computation with spikes. Neural Comput. 18, 245-282. doi: 10.1162/089976606775093882.
-
(2006)
Neural Comput
, vol.18
, pp. 245-282
-
-
Izhikevich, E.M.1
-
18
-
-
33845642736
-
Towards cortex sized artificial neural systems
-
doi: 10.1016/j.neunet.2006.05.029
-
Johansson, C., and Lansner, A. (2007). Towards cortex sized artificial neural systems. Neural Netw. 20, 48-61. doi: 10.1016/j.neunet.2006.05.029.
-
(2007)
Neural Netw
, vol.20
, pp. 48-61
-
-
Johansson, C.1
Lansner, A.2
-
19
-
-
0030115492
-
Energy efficient neural codes
-
doi: 10.1162/neco.1996.8.3.531
-
Levy, W. B., and Baxter, R. A. (1996). Energy efficient neural codes. Neural Comput. 8, 531-543. doi: 10.1162/neco.1996.8.3.531.
-
(1996)
Neural Comput
, vol.8
, pp. 531-543
-
-
Levy, W.B.1
Baxter, R.A.2
-
20
-
-
0038114082
-
-
Cambridge, MA: MIT Press
-
Liu, S., Kramer, J., Indiveri, G., Delbrück, T., and Douglas, R. (2002). Analog VLSI: Circuits and Principles. Cambridge, MA: MIT Press.
-
(2002)
Analog VLSI: Circuits and Principles
-
-
Liu, S.1
Kramer, J.2
Indiveri, G.3
Delbrück, T.4
Douglas, R.5
-
21
-
-
0037270342
-
Duality of rate coding and temporal coding in multilayered feedforward networks
-
doi: 10.1162/089976603321043711
-
Masuda, N., and Aihara, K. (2003). Duality of rate coding and temporal coding in multilayered feedforward networks. Neural Comput. 15, 103-125. doi: 10.1162/089976603321043711.
-
(2003)
Neural Comput
, vol.15
, pp. 103-125
-
-
Masuda, N.1
Aihara, K.2
-
22
-
-
63249097213
-
A generalized linear integrate-and-fire neural model produces diverse spiking behaviors
-
doi: 10.1162/neco.2008.12-07-680
-
Mihalas, S., and Niebur, E. (2009). A generalized linear integrate-and-fire neural model produces diverse spiking behaviors. Neural Comput. 21, 704-718. doi: 10.1162/neco.2008.12-07-680.
-
(2009)
Neural Comput
, vol.21
, pp. 704-718
-
-
Mihalas, S.1
Niebur, E.2
-
23
-
-
84876923734
-
Programming time-multiplexed reconfigurable hardware using a scalable neuromorphic compiler
-
doi: 10.1109/TNNLS.2012.2191795
-
Minkovich, K., Srinivasa, N., Cruz-Albrecht, J. M., Cho, Y., and Nogin, A. (2012). Programming time-multiplexed reconfigurable hardware using a scalable neuromorphic compiler. IEEE Trans. Neural Netw. Learn. Syst. 23, 889-901. doi: 10.1109/TNNLS.2012.2191795.
-
(2012)
IEEE Trans. Neural Netw. Learn. Syst
, vol.23
, pp. 889-901
-
-
Minkovich, K.1
Srinivasa, N.2
Cruz-Albrecht, J.M.3
Cho, Y.4
Nogin, A.5
-
24
-
-
33846192848
-
A feed-forward time-multiplexed neural network with mixed-signal neuron-synapse arrays
-
doi: 10.1016/j.mee.2006.02.014
-
Mirhassani, M., Ahmadi, M., and Miller, W. C. (2007). A feed-forward time-multiplexed neural network with mixed-signal neuron-synapse arrays. Microelectron. Eng. 84, 300-307. doi: 10.1016/j.mee.2006.02.014.
-
(2007)
Microelectron. Eng
, vol.84
, pp. 300-307
-
-
Mirhassani, M.1
Ahmadi, M.2
Miller, W.C.3
-
25
-
-
0035392692
-
A micropower class-AB CMOS log-domain filter for DECT applications
-
doi: 10.1109/4.933462
-
Python, D., and Enz, C. C. (2001). A micropower class-AB CMOS log-domain filter for DECT applications. IEEE J. Solid State Circuits 36, 1067-1075. doi: 10.1109/4.933462.
-
(2001)
IEEE J. Solid State Circuits
, vol.36
, pp. 1067-1075
-
-
Python, D.1
Enz, C.C.2
-
26
-
-
79959452713
-
'Hardware system for biologically realistic, plastic, and real-time spiking neural network simulations'
-
doi: 10.1109/IJCNN.2010.5596979.
-
Saighi, S., Levi, T., Belhadj, B., Malot, O., and Tomas, J. (2010). "Hardware system for biologically realistic, plastic, and real-time spiking neural network simulations," in 2010 International Joint Conference on Neural Networks (Barcelona), 1-7. doi: 10.1109/IJCNN.2010.5596979.
-
(2010)
2010 International Joint Conference on Neural Networks (Barcelona)
, pp. 1-7
-
-
Saighi, S.1
Levi, T.2
Belhadj, B.3
Malot, O.4
Tomas, J.5
-
27
-
-
56349166622
-
'Wafer-scale integration of analog neural networks'
-
(IEEE World Congr. Comput. Intell.) (Hong Kong). doi: 10.1109/IJCNN.2008.4633828.
-
Schemmel, J., Fieres, J., and Meier, K. (2008). "Wafer-scale integration of analog neural networks," in 2008 International Joint Conference on Neural Networks (IEEE World Congr. Comput. Intell.) (Hong Kong), 431-438. doi: 10.1109/IJCNN.2008.4633828.
-
(2008)
2008 International Joint Conference on Neural Networks
, pp. 431-438
-
-
Schemmel, J.1
Fieres, J.2
Meier, K.3
-
28
-
-
84862237704
-
VLSI implementation of a 2.8 Gevent/s packet-based AER interface with routing and event sorting functionality
-
doi: 10.3389/fnins.2011.00117
-
Scholze, S., Schiefer, S., Partzsch, J., Hartmann, S., Mayr, C. G., Höppner, S., et al. (2011). VLSI implementation of a 2.8 Gevent/s packet-based AER interface with routing and event sorting functionality. Front. Neurosci. 5:117. doi: 10.3389/fnins.2011.00117.
-
(2011)
Front. Neurosci
, vol.5
, pp. 117
-
-
Scholze, S.1
Schiefer, S.2
Partzsch, J.3
Hartmann, S.4
Mayr, C.G.5
Höppner, S.6
-
29
-
-
84865081970
-
'Exploiting device mismatch in neuromorphic VLSI systems to implement axonal delays'
-
doi: 10.1109/IJCNN.2012.6252636.
-
Sheik, S., Chicca, E., and Indiveri, G. (2012). "Exploiting device mismatch in neuromorphic VLSI systems to implement axonal delays," in 2012 International Joint Conference on Neural Networks (Brisbane, QLD), 1-6. doi: 10.1109/IJCNN.2012.6252636.
-
(2012)
2012 International Joint Conference on Neural Networks (Brisbane, QLD)
, pp. 1-6
-
-
Sheik, S.1
Chicca, E.2
Indiveri, G.3
-
30
-
-
84880713240
-
'Spatio-temporal spike pattern classification in neuromorphic systems'
-
eds N. F. Lepora, A. Mura, H G. Krapp, P. F. M. J. Verschure, and T. J. Prescott (Heidelberg: Springer), doi: 10.1007/978-3-642-39802-5_23
-
Sheik, S., Pfeiffer, M., Stefanini, F., and Indiveri, G. (2013). "Spatio-temporal spike pattern classification in neuromorphic systems," in Biomimetic and Biohybrid Systems, eds N. F. Lepora, A. Mura, H. G. Krapp, P. F. M. J. Verschure, and T. J. Prescott (Heidelberg: Springer), 262-273. doi: 10.1007/978-3-642-39802-5_23.
-
(2013)
Biomimetic and Biohybrid Systems
, pp. 262-273
-
-
Sheik, S.1
Pfeiffer, M.2
Stefanini, F.3
Indiveri, G.4
-
31
-
-
0035380719
-
Rate coding versus temporal order coding: what the retinal ganglion cells tell the visual cortex
-
doi: 10.1162/08997660152002852
-
Van Rullen, R., and Thorpe, S. J. (2001). Rate coding versus temporal order coding: what the retinal ganglion cells tell the visual cortex. Neural Comput. 13, 1255-1283. doi: 10.1162/08997660152002852.
-
(2001)
Neural Comput
, vol.13
, pp. 1255-1283
-
-
Van Rullen, R.1
Thorpe, S.J.2
-
32
-
-
33846098196
-
Dynamically reconfigurable silicon array of spiking neurons with conductance-based synapses
-
doi: 10.1109/TNN.2006.883007
-
Vogelstein, R. J., Mallik, U., Vogelstein, J. T., and Cauwenberghs, G. (2007). Dynamically reconfigurable silicon array of spiking neurons with conductance-based synapses. IEEE Trans. Neural Netw. 18, 253-265. doi: 10.1109/TNN.2006.883007.
-
(2007)
IEEE Trans. Neural Netw
, vol.18
, pp. 253-265
-
-
Vogelstein, R.J.1
Mallik, U.2
Vogelstein, J.T.3
Cauwenberghs, G.4
-
33
-
-
84883392520
-
'An improved aVLSI axon with programmable delay using spike timing dependent delay plasticity'
-
(IEEE) (Beijing)
-
Wang, R., Cohen, G., Hamilton, T. J., Tapson, J., and Van Schaik, A. (2013a). "An improved aVLSI axon with programmable delay using spike timing dependent delay plasticity," in 2013 IEEE International Symposium of Circuits and Systems (ISCAS) (IEEE) (Beijing), 2-5.
-
(2013)
2013 IEEE International Symposium of Circuits and Systems (ISCAS)
, pp. 2-5
-
-
Wang, R.1
Cohen, G.2
Hamilton, T.J.3
Tapson, J.4
Van Schaik, A.5
-
34
-
-
84878868253
-
An FPGA implementation of a polychronous spiking neural network with delay adaptation
-
doi: 10.3389/fnins.2013.00014
-
Wang, R., Cohen, G., Stiefel, K. M., Hamilton, T. J., Tapson, J., and van Schaik, A. (2013b). An FPGA implementation of a polychronous spiking neural network with delay adaptation. Front. Neurosci. 7:14. doi: 10.3389/fnins.2013.00014.
-
(2013)
Front. Neurosci.
, vol.7
, pp. 14
-
-
Wang, R.1
Cohen, G.2
Stiefel, K.M.3
Hamilton, T.J.4
Tapson, J.5
van Schaik, A.6
-
35
-
-
84863278218
-
'An analogue VLSI implementation of polychronous spiking neural networks'
-
doi: 10.1109/ISSNIP.2011.6146572.
-
Wang, R., Tapson, J., Hamilton, T. J., and van Schaik, A. (2011). "An analogue VLSI implementation of polychronous spiking neural networks," in 2011 Seventh International Conference on Intelligent Sensors, Sensor Networks and Information Processing (IEEE) (Adelaide, SA), 97-102. doi: 10.1109/ISSNIP.2011.6146572.
-
(2011)
2011 Seventh International Conference on Intelligent Sensors, Sensor Networks and Information Processing (IEEE) (Adelaide, SA)
, pp. 97-102
-
-
Wang, R.1
Tapson, J.2
Hamilton, T.J.3
van Schaik, A.4
-
37
-
-
77956000847
-
'Log-domain time-multiplexed realization of dynamical conductance-based synapses'
-
doi: 10.1109/ISCAS.2010.5537114.
-
Yu, T., and Cauwenberghs, G. (2010). "Log-domain time-multiplexed realization of dynamical conductance-based synapses," in Proceedings of 2010 IEEE International Symposium on Circuits System (Paris), 2558-2561. doi: 10.1109/ISCAS.2010.5537114.
-
(2010)
Proceedings of 2010 IEEE International Symposium on Circuits System (Paris)
, pp. 2558-2561
-
-
Yu, T.1
Cauwenberghs, G.2
-
38
-
-
79951517328
-
Performance/price estimates for cortex-scale hardware: a design space exploration
-
doi: 10.1016/j.neunet.2010.12.003
-
Zaveri, M. S., and Hammerstrom, D. (2011). Performance/price estimates for cortex-scale hardware: a design space exploration. Neural Netw. 24, 291-304. doi: 10.1016/j.neunet.2010.12.003.
-
(2011)
Neural Netw
, vol.24
, pp. 291-304
-
-
Zaveri, M.S.1
Hammerstrom, D.2
|