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Volumn , Issue , 2008, Pages 483-486

Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTELLIGENT AGENTS; LOW POWER ELECTRONICS; NETWORK-ON-CHIP; NEURAL NETWORKS;

EID: 54949132181     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2008.4629989     Document Type: Conference Paper
Times cited : (23)

References (19)
  • 3
    • 54949113138 scopus 로고    scopus 로고
    • A Ghani A, J Harkin et al.; Area Efficient Architecture for Large Scale Implementation of Biologically Plausible Spiking Neural Networks on Reconfigurable Hardware, FPL, 2006
    • A Ghani A, J Harkin et al.; "Area Efficient Architecture for Large Scale Implementation of Biologically Plausible Spiking Neural Networks on Reconfigurable Hardware", FPL, 2006
  • 4
    • 54949094996 scopus 로고    scopus 로고
    • Novel Approach for the Implementation of Large-Scale SNNs on FPGAs
    • B Glackin et al., "Novel Approach for the Implementation of Large-Scale SNNs on FPGAs", Artificial NNs Conference, 2005
    • (2005) Artificial NNs Conference
    • Glackin, B.1
  • 5
    • 54949152984 scopus 로고    scopus 로고
    • An FPGA platform for on-line topology exploration of SNNs
    • A Upegui et al; "An FPGA platform for on-line topology exploration of SNNs", Micros & Microsystems, 29(5), 2005
    • (2005) Micros & Microsystems , vol.29 , Issue.5
    • Upegui, A.1
  • 6
    • 34548604536 scopus 로고    scopus 로고
    • Implementing SNNs for Real-Time Signal-Processing and Control Applications: A Model-Validated FPGA Approach
    • MJ Pearson et al., "Implementing SNNs for Real-Time Signal-Processing and Control Applications: A Model-Validated FPGA Approach", IEEE Trans, on Neural Nets, 18(5), 2007
    • (2007) IEEE Trans, on Neural Nets , vol.18 , Issue.5
    • Pearson, M.J.1
  • 7
    • 35649003747 scopus 로고    scopus 로고
    • Challenges for large-scale implementations of SNNs on FPGAs
    • LP Maguire, J Harkin et al.; "Challenges for large-scale implementations of SNNs on FPGAs", Neurocomputing, 71(1-3), pp. 13-29, 2007
    • (2007) Neurocomputing , vol.71 , Issue.1-3 , pp. 13-29
    • Maguire, L.P.1    Harkin, J.2
  • 8
    • 0036149420 scopus 로고    scopus 로고
    • Networks on Chips: A New SoC Paradigm
    • Jan
    • L Benini, G DeMicheli, "Networks on Chips: A New SoC Paradigm", IEEE Computers, pp. 70-78, Jan 2002
    • (2002) IEEE Computers , pp. 70-78
    • Benini, L.1    DeMicheli, G.2
  • 9
    • 33846098196 scopus 로고    scopus 로고
    • Dynamically Reconfigurable Silicon Array of Spiking Neurons with Conductance-Based Synapses
    • RJ Vogelstein et al., "Dynamically Reconfigurable Silicon Array of Spiking Neurons with Conductance-Based Synapses", IEEE Trans. Neural Nets, 18 (1), pp. 253 265, 2007
    • (2007) IEEE Trans. Neural Nets , vol.18 , Issue.1 , pp. 253-265
    • Vogelstein, R.J.1
  • 10
    • 6344263535 scopus 로고    scopus 로고
    • Design of FPGA Interconnect for Multilevel Metallization, IEEE Tran
    • A DeHon, R Rubin, "Design of FPGA Interconnect for Multilevel Metallization", IEEE Tran. VLSI Sys., 12(10), 2004
    • (2004) VLSI Sys , vol.12 , Issue.10
    • DeHon, A.1    Rubin, R.2
  • 11
    • 33746461451 scopus 로고    scopus 로고
    • Using Bus-Based Connections to Improve FPGA Density for Implementing Data-path Circuits
    • J Rose, et al. "Using Bus-Based Connections to Improve FPGA Density for Implementing Data-path Circuits", IEEE Transactions VLSI Systems, 14(5), pp. 462-473, 2006
    • (2006) IEEE Transactions VLSI Systems , vol.14 , Issue.5 , pp. 462-473
    • Rose, J.1
  • 12
    • 44649182862 scopus 로고    scopus 로고
    • CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs
    • S Jovanovic et al. "CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs", FPL, 2007, pp. 753 756
    • (2007) FPL , pp. 753-756
    • Jovanovic, S.1
  • 13
    • 54949135643 scopus 로고    scopus 로고
    • Virtual Synaptic Interconnect Using an Asynchronous Network-on-Chip
    • June 1st-6th
    • th, 2008
    • (2008) WCCI
    • Rast, A.D.1
  • 14
    • 48149083974 scopus 로고    scopus 로고
    • artNoC - A Novel Multi-Functional Router Architecture for Organic Computing
    • C Schuck et al., "artNoC - A Novel Multi-Functional Router Architecture for Organic Computing", FPL, 2007, pp. 371-376
    • (2007) FPL , pp. 371-376
    • Schuck, C.1
  • 15
    • 54949118631 scopus 로고    scopus 로고
    • Mixed-Mode Analog NN Using Current-Steering Synapses
    • J Schemmel et. al, "Mixed-Mode Analog NN Using Current-Steering Synapses", Analog Circ. & Signal Proa, Vol. 38, 2004
    • (2004) Analog Circ. & Signal Proa , vol.38
    • Schemmel, J.1    et., al.2
  • 16
    • 54949093498 scopus 로고    scopus 로고
    • Novel Interconnect Strategy for Large Scale Implementations of NNs
    • J Harkin et al. "Novel Interconnect Strategy for Large Scale Implementations of NNs", IEEE Soft Comp. in Indust. App, 2007
    • (2007) IEEE Soft Comp. in Indust. App
    • Harkin, J.1
  • 17
    • 54949090271 scopus 로고    scopus 로고
    • A Programmable Facilitating Synapse Device
    • Y Chen, LJ McDaid et al, "A Programmable Facilitating Synapse Device", WCCI, June lst-6th, 2008
    • (2008) WCCI, June lst-6th
    • Chen, Y.1    McDaid, L.J.2
  • 18
    • 54949124486 scopus 로고    scopus 로고
    • A Silicon Synapse Based on A Charge Transfer Device for SNN
    • May
    • Y Chen, et al. "A Silicon Synapse Based on A Charge Transfer Device for SNN", Int. Symp. on Neural Nets, May 2006
    • (2006) Int. Symp. on Neural Nets
    • Chen, Y.1
  • 19
    • 54949087775 scopus 로고    scopus 로고
    • Hardwired NoCs in FPGAs to unify Data & Config. Interconnects
    • April
    • K Goossens, et al., "Hardwired NoCs in FPGAs to unify Data & Config. Interconnects", Int Symp. on NoCs, April 2008
    • (2008) Int Symp. on NoCs
    • Goossens, K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.