DELTRON: Neuromorphic architectures for delay based learning

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn , Issue , 2012, Pages 304-307

  Hussain, Shaista ^a   Basu, Arindam ^a   Wang, Mark ^b   Hamilton, Tara Julia ^b  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b UNIVERSITY OF NEW SOUTH WALES   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

CORE CIRCUIT; HARDWARE IMPLEMENTATIONS; LEARNING RULES; MEMORY CAPACITY; MIXED SIGNAL; NEUROMORPHIC; NEUROMORPHIC ARCHITECTURES; RECONFIGURABLE; SPATIO-TEMPORAL; SPICE SIMULATIONS; SPIKE PATTERNS; SPIKING NEURAL NETWORKS;

DIGITAL TO ANALOG CONVERSION; HARDWARE; MEMORY ARCHITECTURE; NEURAL NETWORKS; SPICE;

RECONFIGURABLE ARCHITECTURES;

EID: 84874185723     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCCAS.2012.6419032     Document Type: Conference Paper

References (11)

1. V. Chan, S. C. Liu and A. Van Schaik, "AER EAR: A Matched Silicon Cochlea Pair with Address Event Representation Interface," IEEE Trans. Circuits And Systems-I, vol. 54, no. 1, pp. 48-59, 2007.
2. P. Lichtsteiner, C. Posch and T. Delbruck, "A 128X128 120 dB 15 us Latency Asynchronous Temporal Contrast Vision Sensor," IEEE Journal of Solid-State Circuits, vol. 43, no. 2, pp. 566-76, 2008.
3. G. Indiveri et.al., "Neuromorphic Silicon Neuron Circuits," Frontiers in Neuroscience, vol. 5, 2011, doi : 10.3389/fnins.2011.00073.
4. C. Bartolozzi and G. Indiveri, "Synaptic Dynamics in Analog VLSI," Neural Computation, vol. 19, no. 10, pp. 2581-2603, 2007.
5. A. Basu, S. Ramakrishnan, C. Petre, S. Koziol S. Brink and P. Hasler,"Neural Dynamics in Reconfigurable Silicon," IEEE Trans. on Biomedical Circuits and Systems. vol. 4, no. 5, pp. 311-19, Oct. 2010.
6. E. Izhikevich, "Polychronization: Computation with Spikes," Neural Computation, vol.18, pp. 245-282, 2006.
7. R. Wang, C. Jin, A. McEwan and A. VanSchaik, "A programmable axonal propagation delay circuit for time-delay spiking neural networks," in Proc. IEEE ISCAS, pp. 869-72, 2011.
8. R. Gutig and H. Sompolinsky, "The tempotron: a neuron that leanrs spike timing based decisions," Nature Neuroscience, vol. 9, pp. 420-428, 2006.
9. M. Mahowald, "VLSI Analogs of Neuronal Visual Processing: A Synthesis of Form and Function," Ph.D. Dissertation, California Inst. of Tech., 1992.
10. P. Livi and G. Indiveri, "A current-mode conductance-based silicon neuron for Address-Event neuromorphic systems," in Proc. of IEEE Intl. Symp. Circ. and Sys, pp. 2898-2901, 2009.
11. C. Bartolozzi and G. Indiveri, "Synaptic dynamics in analog VLSI," Neural Computation, vol. 19, no. 10, pp. 2581-2603, 2007.