Programming time-multiplexed reconfigurable hardware using a scalable neuromorphic compiler

IEEE Transactions on Neural Networks and Learning Systems

Volumn 23, Issue 6, 2012, Pages 889-901

  Minkovich, Kirill ^a   Srinivasa, Narayan ^a   Cruz Albrecht, Jose M ^a   Cho, Youngkwan ^a   Nogin, Aleksey ^a  

^a Hughes Aircraft Co   (United States)

Author keywords

Neuromorphic systems; neurons; routing; scalable architecture; synapses

Indexed keywords

COMPLEMENTARY METAL OXIDE SEMICONDUCTORS; NEURAL ARCHITECTURES; NEUROMORPHIC HARDWARES; NEUROMORPHIC SYSTEMS; PROPOSED ARCHITECTURES; ROUTING; SCALABLE ARCHITECTURES; SYNAPSES;

HARDWARE; NEURAL NETWORKS; NEURONS; SCALABILITY;

PROGRAM COMPILERS;

ACTION POTENTIAL; ANIMAL; ARTIFICIAL NEURAL NETWORK; BIOLOGICAL MODEL; COMPUTER PROGRAM; COMPUTER SIMULATION; DEVICE FAILURE ANALYSIS; DEVICES; EQUIPMENT DESIGN; HUMAN; NERVE CELL; NERVE CELL NETWORK; PHYSIOLOGY; SEMICONDUCTOR; SIGNAL PROCESSING;

ACTION POTENTIALS; ANIMALS; COMPUTER SIMULATION; EQUIPMENT DESIGN; EQUIPMENT FAILURE ANALYSIS; HUMANS; MODELS, NEUROLOGICAL; NERVE NET; NEURAL NETWORKS (COMPUTER); NEURONS; SEMICONDUCTORS; SIGNAL PROCESSING, COMPUTER-ASSISTED; SOFTWARE;

EID: 84876923734     PISSN: 2162237X     EISSN: 21622388     Source Type: Journal    
DOI: 10.1109/TNNLS.2012.2191795     Document Type: Article

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