-
1
-
-
34547229372
-
A reconfigurable design-for-debug infrastructure for SoCs
-
M. Abramovici, "A Reconfigurable Design-for-Debug Infrastructure for SoCs", Proc. IEEE/ACM Design Automation Confi., pp. 7-12, 2006.
-
(2006)
Proc. IEEE/ACM Design Automation Confi.
, pp. 7-12
-
-
Abramovici, M.1
-
2
-
-
80052647494
-
Reaching coverage closure in post-silicon validation
-
A. Adir, A. Nahir, A. Ziv, C. Meissner, and J. Schumann, "Reaching Coverage Closure in Post-Silicon Validation", Proc. Haifa Verification Conf., pp. 60-74, 2010.
-
(2010)
Proc. Haifa Verification Conf.
, pp. 60-74
-
-
Adir, A.1
Nahir, A.2
Ziv, A.3
Meissner, C.4
Schumann, J.5
-
3
-
-
84863541515
-
A unified methodology for pre-silicon verification and post-silicon validation
-
A. Adir, et al., "A Unified Methodology for Pre-Silicon Verification and Post-silicon Validation", Proc. IEEE/ACM Design, Automation and Test in Europe Conf., pp. 1-6, 2011.
-
(2011)
Proc. IEEE/ACM Design, Automation and Test in Europe Conf.
, pp. 1-6
-
-
Adir, A.1
-
4
-
-
80052663051
-
Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor
-
A. Adir, et al. "Leveraging Pre-Silicon Verification Resources for the Post-Silicon Validation of the IBM POWER7 Processor", Proc. IEEE/ACM Design Automation Conf. pp. 569-574. 2011.
-
(2011)
Proc. IEEE/ACM Design Automation Conf.
, pp. 569-574
-
-
Adir, A.1
-
5
-
-
0029230835
-
Test program generation for functional verification of PowerPC processors in IBM
-
A. Aharon, et al., "Test Program Generation for Functional Verification of PowerPC Processors in IBM", Proc. IEEE/ACM Design Automation Conf., pp. 279-285, 1995.
-
(1995)
Proc. IEEE/ACM Design Automation Conf.
, pp. 279-285
-
-
Aharon, A.1
-
6
-
-
76549091946
-
Microprocessor system failures debug and fault isolation methodology
-
M. E. Amyeen, S. Venkataraman, and M. W. Mak, "Microprocessor System Failures Debug and Fault Isolation Methodology", Proc. IEEE Intl. Test Conf., pp. 1-10, 2009.
-
(2009)
Proc. IEEE Intl. Test Conf.
, pp. 1-10
-
-
Amyeen, M.E.1
Venkataraman, S.2
Mak, M.W.3
-
7
-
-
0142206120
-
Validating the intel pentium 4 processor
-
B. Bentley, and R. Gray, "Validating the Intel Pentium 4 Processor", Intel Technology Journal, Vol. 5 No. 1, pp. 1-8, 2001.
-
(2001)
Intel Technology Journal
, vol.5
, Issue.1
, pp. 1-8
-
-
Bentley, B.1
Gray, R.2
-
9
-
-
34548127961
-
Assertion checkers in verification, silicon debug and in-field diagnosis
-
M. Boule, J.-S. Chenard, and Z. Zilic, "Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis", Proc. IEEE Intl. Symp. on Quality Electronic Design, pp. 613-620, 2007.
-
(2007)
Proc. IEEE Intl. Symp. on Quality Electronic Design
, pp. 613-620
-
-
Boule, M.1
Chenard, J.-S.2
Zilic, Z.3
-
10
-
-
48249116687
-
Automated post-silicon debugging and repair
-
K.-H. Chang, I. L. Markov, and V. Bertacco, "Automated Post-Silicon Debugging and Repair", Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design, pp. 91-98, 2007.
-
(2007)
Proc. IEEE/ACM Intl. Conf. on Computer-aided Design
, pp. 91-98
-
-
Chang, K.-H.1
Markov, I.L.2
Bertacco, V.3
-
11
-
-
84864065356
-
NuTAB-BackSpace: Rewriting to normalize non-determinism in post-silicon debug traces
-
F. M. De Paula, A. J. Hu, and A. Nahir, "nuTAB-BackSpace: Rewriting to Normalize Non-Determinism in Post-Silicon Debug Traces", Proc. Intl. Conf. on Computer Aided Verification, pp. 513-531, 2012.
-
(2012)
Proc. Intl. Conf. on Computer Aided Verification
, pp. 513-531
-
-
De Paula, F.M.1
Hu, A.J.2
Nahir, A.3
-
12
-
-
62349108688
-
Post-silicon verification for cache coherence
-
A. DeOrio, A. Bauserman, and V. Bertacco, "Post-Silicon Verification for Cache Coherence", Proc. IEEE Intl. Conf. Computer Design, pp. 348-355, 2008.
-
(2008)
Proc. IEEE Intl. Conf. Computer Design
, pp. 348-355
-
-
De Orio, A.1
Bauserman, A.2
Bertacco, V.3
-
13
-
-
64949118633
-
DACOTA: Post-silicon validation of the memory subsystem in multi-core designs
-
A. DeOrio, I. Wagner, and V. Bertacco, "DACOTA: Post-Silicon Validation of the Memory Subsystem in Multi-Core Designs", Proc. IEEE Intl. Symp. High-Performance Computer Architecture, pp. 405-416, 2009.
-
(2009)
Proc. IEEE Intl. Symp. High-performance Computer Architecture
, pp. 405-416
-
-
De Orio, A.1
Wagner, I.2
Bertacco, V.3
-
14
-
-
0042674307
-
The LINPACK Benchmark: Past, Present and Future
-
J. Dongarra, P. Luszczek, and A. Petitet, "The LINPACK Benchmark: Past, Present and Future", Concurrency and Computation: Practice and Experience. Vol. 15, No. 9, pp. 803-820, 2003.
-
(2003)
Concurrency and Computation: Practice and Experience
, vol.15
, Issue.9
, pp. 803-820
-
-
Dongarra, J.1
Luszczek, P.2
Petitet, A.3
-
15
-
-
35348872682
-
The daikon system for dynamic detection of likely invariants
-
Dec.
-
M. D. Ernst, et al., "The Daikon System for Dynamic Detection of Likely Invariants", Science of Computer Programming, Vol. 69, No. 1-3, pp. 35-45, Dec. 2007.
-
(2007)
Science of Computer Programming
, vol.69
, Issue.1-3
, pp. 35-45
-
-
Ernst, M.D.1
-
16
-
-
34249799055
-
First silicon functional validation and debug of multicore microprocessors
-
T. J. Foster, D. L. Lastor, and P. Singh, "First Silicon Functional Validation and Debug of Multicore Microprocessors", IEEE Trans. Very Large Scale Integration Systems, Vol. 15, No. 5, 2007.
-
(2007)
IEEE Trans. Very Large Scale Integration Systems
, vol.15
, Issue.5
-
-
Foster, T.J.1
Lastor, D.L.2
Singh, P.3
-
17
-
-
58249123841
-
Time-multiplexed online checking: A feasibility study
-
M. Gao, H.-M. Chang, P. Lisherness, and K.-T. Cheng, "Time- Multiplexed Online Checking: A Feasibility Study", Proc. IEEE Asian Test Symp., pp. 371-376, 2008.
-
(2008)
Proc. IEEE Asian Test Symp.
, pp. 371-376
-
-
Gao, M.1
Chang, H.-M.2
Lisherness, P.3
Cheng, K.-T.4
-
18
-
-
27944434746
-
IODINE: A tool to automatically infer dynamic invariants
-
S. Hangal, S. Narayanan, N. Chandra, and S. Chakravorty, "IODINE: A Tool to Automatically Infer Dynamic Invariants", Proc. IEEE/ACM Design Automation Conf., pp. 775-778, 2005.
-
(2005)
Proc. IEEE/ACM Design Automation Conf.
, pp. 775-778
-
-
Hangal, S.1
Narayanan, S.2
Chandra, N.3
Chakravorty, S.4
-
19
-
-
0029195606
-
Architecture Validation for Processors
-
R. C. Ho, C. H. Yang, M. A. Horowitz, and D. L. Dill, "Architecture Validation for Processors", Proc. ACM/IEEE Intl. Symp. Computer Architecture, pp. 404-413, 1995.
-
(1995)
Proc. ACM/IEEE Intl. Symp. Computer Architecture
, pp. 404-413
-
-
Ho, R.C.1
Yang, C.H.2
Horowitz, M.A.3
Dill, D.L.4
-
20
-
-
79951593931
-
QED: Quick error detection tests for effective post-silicon validation
-
T. Hong, et al., "QED: Quick Error Detection Tests for Effective Post-Silicon Validation", Proc. IEEE Intl. Test Conf., pp. 1-10, 2010.
-
(2010)
Proc. IEEE Intl. Test Conf.
, pp. 1-10
-
-
Hong, T.1
-
21
-
-
77952123736
-
A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS
-
J. Howard, et al., "A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS", Proc. IEEE. Intl. Solid-State Circuits Conf., pp. 7-11, 2010.
-
(2010)
Proc. IEEE. Intl. Solid-state Circuits Conf.
, pp. 7-11
-
-
Howard, J.1
-
22
-
-
34547172864
-
The good, the bad, and the ugly of silicon debug
-
D. Josephson, "The Good, the Bad, and the Ugly of Silicon Debug", Proc. IEEE/ACM Design Automation Conf., pp. 3-6, 2006.
-
(2006)
Proc. IEEE/ACM Design Automation Conf.
, pp. 3-6
-
-
Josephson, D.1
-
23
-
-
77956193830
-
Post-silicon validation challenges: How EDA and academia can help
-
J. Keshava, N. Hakim, and C. Prudvi, "Post-silicon Validation Challenges: How EDA and Academia Can Help", Proc. IEEE/ACM Design Automation Conf., pp. 3-7, 2010.
-
(2010)
Proc. IEEE/ACM Design Automation Conf.
, pp. 3-7
-
-
Keshava, J.1
Hakim, N.2
Prudvi, C.3
-
24
-
-
0142216004
-
Diagnosis-based post-silicon timing validation using statistical tools and methodologies
-
A. Krstic, L.-C. Wang, K.-T. Cheng, and T. M. Mak, "Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies", Proc. IEEE Intl. Test Conf., pp. 339-348, 2003.
-
(2003)
Proc. IEEE Intl. Test Conf.
, pp. 339-348
-
-
Krstic, A.1
Wang, L.-C.2
Cheng, K.-T.3
Mak, T.M.4
-
25
-
-
63349096330
-
Functional verification of the IBM system z10 processor chipset
-
C. A. Krygowski, et al., "Functional Verification of the IBM System z10 Processor Chipset", IBM Journal of Research and Development, Vol. 53, No. 1, pp. 1-11, 2009.
-
(2009)
IBM Journal of Research and Development
, vol.53
, Issue.1
, pp. 1-11
-
-
Krygowski, C.A.1
-
26
-
-
84863556903
-
Quick detection of difficult bugs for effective post-silicon validation
-
D. Lin, T. Hong, F. Fallah, N. Hakim, and S. Mitra "Quick Detection of Difficult Bugs for Effective Post-Silicon Validation", Proc. IEEE/ACM Design Automation Conf., pp. 561-566, 2012.
-
(2012)
Proc. IEEE/ACM Design Automation Conf.
, pp. 561-566
-
-
Lin, D.1
Hong, T.2
Fallah, F.3
Hakim, N.4
Mitra, S.5
-
27
-
-
84885605827
-
Overcoming post-silicon validation challenges through quick error detection (QED)
-
D. Lin, et al., "Overcoming Post-Silicon Validation Challenges Through Quick Error Detection (QED)", Proc. IEEE/ACM Design, Automation and Test in Europe Conf., pp. 320-325, 2013.
-
(2013)
Proc. IEEE/ACM Design, Automation and Test in Europe Conf.
, pp. 320-325
-
-
Lin, D.1
-
28
-
-
2942717731
-
Strategies for fault-tolerant space-based computing: Lessons learned from the ARGOS testbed
-
2109-5-2119
-
M. N. Lovellette, et al., "Strategies for Fault-tolerant Space-based Computing: Lessons Learned from the ARGOS Testbed", Proc. Aerospace Conf., pp. 5-2109-5-2119, 2002.
-
(2002)
Proc. Aerospace Conf.
, pp. 5
-
-
Lovellette, M.N.1
-
29
-
-
77956210287
-
Post-silicon validation opportunities, challenges and recent advances
-
S. Mitra, S. A. Seshia, and N. Nicolici, "Post-Silicon Validation Opportunities, Challenges and Recent Advances", Proc. IEEE/ACM Design Automation Conf., pp. 12-17, 2010.
-
(2010)
Proc. IEEE/ACM Design Automation Conf.
, pp. 12-17
-
-
Mitra, S.1
Seshia, S.A.2
Nicolici, N.3
-
30
-
-
0036507790
-
Error detection by duplicated instructions in super-scalar processors
-
N. Oh, P. P. Shirvani, and E. J. McCluskey, "Error Detection by Duplicated Instructions in Super-Scalar Processors", IEEE Trans. on Reliability, Vol. 51, No. 1, pp. 63-75, 2002.
-
(2002)
IEEE Trans. on Reliability
, vol.51
, Issue.1
, pp. 63-75
-
-
Oh, N.1
Shirvani, P.P.2
McCluskey, E.J.3
-
31
-
-
0036472442
-
4I: Error detection by diverse data and duplicated instructions
-
4I: Error Detection by Diverse Data and Duplicated Instructions", IEEE Trans. on Computers, Vol. 51, No. 2, pp. 180-199, 2002.
-
(2002)
IEEE Trans. on Computers
, vol.51
, Issue.2
, pp. 180-199
-
-
Oh, N.1
Mitra, S.2
McCluskey, E.J.3
-
32
-
-
0036507891
-
Control flow checking by software signatures
-
N. Oh, P. P. Shirvani, and E. J. McCluskey, "Control Flow Checking by Software Signatures", IEEE Trans. on Reliability, Vol. 51, No. 1, pp. 111-122, 2002.
-
(2002)
IEEE Trans. on Reliability
, vol.51
, Issue.1
, pp. 111-122
-
-
Oh, N.1
Shirvani, P.P.2
McCluskey, E.J.3
-
34
-
-
70349732867
-
Post-silicon bug localization in processors using instruction footprint recording and analysis (IFRA)
-
S.-B. Park, T. Hong, and S. Mitra, "Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA)", IEEE. Trans. Computer Aided Design Integrated Circuits Systems, Vol. 28, No. 10, pp. 1545-1558, 2009.
-
(2009)
IEEE. Trans. Computer Aided Design Integrated Circuits Systems
, vol.28
, Issue.10
, pp. 1545-1558
-
-
Park, S.-B.1
Hong, T.2
Mitra, S.3
-
35
-
-
77956209773
-
BLoG: Post-silicon bug localization in processors using bug localization graph
-
S.-B. Park, A. Bracy, P. Wang, and S. Mitra, "BLoG: Post-Silicon Bug Localization in Processors Using Bug Localization Graph", Proc. IEEE/ACM Design Automation Conf., pp. 368-373, 2010.
-
(2010)
Proc. IEEE/ACM Design Automation Conf.
, pp. 368-373
-
-
Park, S.-B.1
Bracy, A.2
Wang, P.3
Mitra, S.4
-
36
-
-
34347392507
-
On the cusp of a validation wall
-
P. Patra, "On the Cusp of a Validation Wall", IEEE Design & Test of Computers, Vol. 24, No. 2, pp. 193-196, 2007.
-
(2007)
IEEE Design & Test of Computers
, vol.24
, Issue.2
, pp. 193-196
-
-
Patra, P.1
-
37
-
-
0031652473
-
Random self-test method applications on PowerPCTM microprocessor cache
-
R. Raina, and R. Molyneaux, "Random Self-Test Method Applications on PowerPCTM Microprocessor Cache", Proc. ACM/IEEE Great Lakes Symp. VLSI, pp. 222-229, 1998.
-
(1998)
Proc. ACM/IEEE Great Lakes Symp. VLSI
, pp. 222-229
-
-
Raina, R.1
Molyneaux, R.2
-
38
-
-
84897871801
-
Post-silicon debug - DAC workshop on post-silicon debug: Technologies, methodologies, and best-practices
-
K. Reick, "Post-Silicon Debug - DAC Workshop on Post-Silicon Debug: Technologies, Methodologies, and Best-Practices", IEEE/ACM Design Automation Conf., 2012.
-
(2012)
IEEE/ACM Design Automation Conf.
-
-
Reick, K.1
-
39
-
-
49749135121
-
Automatic generation of complex properties for hardware designs
-
F. Rogin, T. Klotz, G. Fey, R. Drechsler, and S. Rulke, "Automatic Generation of Complex Properties for Hardware Designs", Proc. IEEE/ACM Design Automation Conf., pp. 545-548, 2008.
-
(2008)
Proc. IEEE/ACM Design Automation Conf.
, pp. 545-548
-
-
Rogin, F.1
Klotz, T.2
Fey, G.3
Drechsler, R.4
Rulke, S.5
-
40
-
-
77953089806
-
GoldMine: Automatic assertion generation using data mining and static analysis
-
S. Vasudevan, et al., "GoldMine: Automatic Assertion Generation Using Data Mining and Static Analysis", Proc. IEEE/ACM Design, Automation, Test in Europe Conf., pp. 626-629, 2010.
-
(2010)
Proc. IEEE/ACM Design, Automation, Test in Europe Conf.
, pp. 626-629
-
-
Vasudevan, S.1
-
41
-
-
0142153743
-
Collection of high-level microprocessor bugs from formal verification of pipelined and superscalar designs
-
M. N. Velev, "Collection of High-Level Microprocessor Bugs from Formal Verification of Pipelined and Superscalar Designs", Proc. IEEE Intl. Test Conf., pp. 138-147, 2003.
-
(2003)
Proc. IEEE Intl. Test Conf.
, pp. 138-147
-
-
Velev, M.N.1
-
42
-
-
0029179077
-
The SPLASH-2 programs: Characterization and methodological considerations
-
S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta, "The SPLASH-2 Programs: Characterization and Methodological Considerations", Proc. ACM/IEEE Intl. Symp. Computer Architecture, pp. 24-36, 1995.
-
(1995)
Proc. ACM/IEEE Intl. Symp. Computer Architecture
, pp. 24-36
-
-
Woo, S.C.1
Ohara, M.2
Torrie, E.3
Singh, J.P.4
Gupta, A.5
-
43
-
-
62349132176
-
Reversi: Post-silicon validation system for modern microprocessors
-
I. Wagner, and V. Bertacco, "Reversi: Post-Silicon Validation System for Modern Microprocessors", Proc. IEEE Intl. Conf. Computer Design, pp. 307-314, 2008.
-
(2008)
Proc. IEEE Intl. Conf. Computer Design
, pp. 307-314
-
-
Wagner, I.1
Bertacco, V.2
-
44
-
-
51549120034
-
Addressing post-silicon validation challenges: Leverage validation & test synergy
-
Keynote
-
S. Yerramilli, "Addressing Post-Silicon Validation Challenges: Leverage Validation & Test Synergy", Keynote, IEEE Intl. Test Conf., 2006.
-
(2006)
IEEE Intl. Test Conf.
-
-
Yerramilli, S.1
|