Post-Silicon verification for cache coherence

26th IEEE International Conference on Computer Design 2008, ICCD

Volumn , Issue , 2008, Pages 348-355

  DeOrio, Andrew ^a   Bauserman, Adam ^a   Bertacco, Valeria ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA OVERHEADS; CACHE COHERENCE PROTOCOLS; CACHE COHERENCES; COHERENCE PROTOCOLS; COMPACT ENCODING; DETECTION AND DIAGNOSIS; FUNCTIONAL ERRORS; HARDWARE PROTOTYPES; MEMORY OVERHEADS; MEMORY RESOURCES; MEMORY SUBSYSTEMS; MODERN PROCESSORS; MULTI CORES; MULTI-CORE SYSTEMS; MULTICORE DESIGNS; POST SILICONS; RUN-TIME; VERIFICATION RESULTS;

DESIGN; ERRORS; MICROPROCESSOR CHIPS;

NONMETALS;

EID: 62349108688     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2008.4751884     Document Type: Conference Paper

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