Random self-test method applications on PowerPCTM microprocessor caches

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1998, Pages 222-229

  Raina, Rajesh ^a   Molyneaux, Robert ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; MICROPROCESSOR CHIPS; RANDOM PROCESSES;

HIGH LEVEL DESIGN VALIDATION; PSEUDO RANDOM TESTING;

INTEGRATED CIRCUIT TESTING;

EID: 0031652473     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)