Reversi: Post-Silicon validation system for modern microprocessors

26th IEEE International Conference on Computer Design 2008, ICCD

Volumn , Issue , 2008, Pages 307-314

  Wagner, Ilya ^a   Bertacco, Valeria ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL SIMULATIONS; DESIGN COMPLEXITY; EXECUTION PERFORMANCE; FINAL STATE; GENERATION TIME; HARDWARE PROTOTYPES; MANUFACTURING DEFECTS; MANUFACTURING PROCESS; MICROPROCESSOR DESIGNS; MODERN MICROPROCESSORS; NOVEL SOLUTIONS; POST SILICONS; RANDOM TESTS; SPEED-UP; TIME-TO-MARKET WINDOWS;

ARCHITECTURE; DESIGN; MICROPROCESSOR CHIPS; NONMETALS;

ARCHITECTURAL DESIGN;

EID: 62349132176     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2008.4751878     Document Type: Conference Paper

References (16)

1. Constrained-random test generation and functional coverage with Vera. Technical report, Synopsys, Inc, Feb. 2003.
2. Revision Guide for AMD Athlon 64 and AMD Opteron Processors, Aug. 2005.
3. Intel Core2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update, Nov. 2007.
4. Intel Core2 Extreme Quad-Core Processor QX6000 Sequence and Intel Core2 Quad Processor Q6000 Sequence, Nov. 2007.
5. The M5 simulator system, Nov. 2007. http://www.m5sim.org.
6. The open source IA-32 emulation project, Sept. 2007. http://bochs. sourceforge.net/.
7. A. Adir et al. Genesys-pro: Innovations in test program generation for functional processor verification. IEEE Design & Test of Computers, 21(2):84-93, Mar. 2004.
8. B. Bentley and R. Gray. Validating the Intel Pentium 4 microprocessor. Intel Technology Journal, Q1, pages 1-8, 2001.
9. K. H. Bierman et al. U.S. Patent no. 7133818: Method and apparatus for accelerated post-silicon testing and random number generation, Nov. 2006.
10. T. Litt. Support for debugging in the Alpha 21364 microprocessor. In International Test Conference, Oct. 2002.
11. M. L. Bushnell, V. D. Agrawal. Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI circuits. Springer, 2000.
12. M. Melani et al. An integrated flow from pre-silicon simulation to post-silicon verification. In Research in Microelectronics and Electronics 2006, Ph. D., pages 205-208, June 2006.
13. P. T. Barch et al. U.S. Patent no. 5923836: Testing integrated circuit designs on a computer simulation using modified serialized scan patterns, Nov. 2006.
14. R. Emek et al. X-Gen: A random test-case generator for systems and SoCs. In International Workshop on High Level Design Validation and Test, pages 145 150, Oct. 2002.
15. R. Raina and R. Molyneaux. Random self-test method - applications on PowerPC microprocessor caches. In Proceedings of the Great Lakes Symposium on VLSI, Feb. 1998.
16. H. Rotithor. Post-silicon validation methodology for microprocessors. IEEE Design & Test of Computers, 17(4):77-88, Oct. 2000.