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Volumn , Issue , 2013, Pages 542-553

EnergySmart: Toward energy-efficient manycores for Near-Threshold Computing

Author keywords

[No Author keywords available]

Indexed keywords

ASSIGNMENT STRATEGIES; ENERGY EFFICIENT; FINE GRAINS; HIGH SENSITIVITY; MULTIPLE FREQUENCY; NEAR THRESHOLDS; NEAR-THRESHOLD COMPUTING; SHORT-INTERVAL;

EID: 84880303483     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2013.6522348     Document Type: Conference Paper
Times cited : (58)

References (37)
  • 1
    • 84880279705 scopus 로고    scopus 로고
    • http://www.intel.com/Assets/en-US/PDF/designguide/321736.pdf.
  • 3
    • 33748535403 scopus 로고    scopus 로고
    • High-performance CMOS variability in the 65-nm regime and beyond
    • July/September
    • K. Bernstein et al., "High-Performance CMOS Variability in the 65-nm Regime and Beyond," in IBM Journal of Research and Development, July/September 2006.
    • (2006) IBM Journal of Research and Development
    • Bernstein, K.1
  • 4
    • 33745766236 scopus 로고    scopus 로고
    • Parameter variations and impact on circuits and microarchitecture
    • S. Borkar et al., "Parameter Variations and Impact on Circuits and Microarchitecture," in Design Automation Conference, 2003.
    • (2003) Design Automation Conference
    • Borkar, S.1
  • 5
    • 58149267845 scopus 로고    scopus 로고
    • Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance
    • January
    • K. Bowman et al., "Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance," Journal of Solid-State Circuits, January 2009.
    • (2009) Journal of Solid-State Circuits
    • Bowman, K.1
  • 6
    • 0000732463 scopus 로고
    • A limited memory algorithm for bound constrained optimization
    • R. H. Byrd et al., "A Limited Memory Algorithm for Bound Constrained Optimization," SIAM Journal of Scientific Computing, 1995.
    • (1995) SIAM Journal of Scientific Computing
    • Byrd, R.H.1
  • 7
    • 75649121827 scopus 로고    scopus 로고
    • Practical strategies for power-efficient computing technologies
    • February
    • L. Chang et al., "Practical Strategies for Power-Efficient Computing Technologies," Proceedings of the IEEE, February 2010.
    • (2010) Proceedings of the IEEE
    • Chang, L.1
  • 8
    • 77957980887 scopus 로고    scopus 로고
    • A fully-integrated switched-capacitor 2:1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm2
    • June
    • L. Chang et al., "A Fully-Integrated Switched-Capacitor 2:1 Voltage Converter with Regulation Capability and 90% Efficiency at 2.3A/mm2," in Symposium on VLSI Circuits, June 2010.
    • (2010) Symposium on VLSI Circuits
    • Chang, L.1
  • 10
    • 0016116644 scopus 로고
    • Design of Ion-Implanted MOSFETs with very small physical dimensions
    • October
    • R. Dennard et al., "Design of Ion-Implanted MOSFETs with Very Small Physical Dimensions," in Journal of Solid-State Circuits, October 1974.
    • (1974) Journal of Solid-State Circuits
    • Dennard, R.1
  • 11
    • 78650896343 scopus 로고    scopus 로고
    • Within-die variation-aware dynamic-voltage-frequency-scalingwith optimal core allocation and thread hopping for the 80-core teraflops processor
    • January
    • S. Dighe et al., "Within-Die Variation-Aware Dynamic-Voltage- Frequency-ScalingWith Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor," Journal of Solid-State Circuits, January 2011.
    • (2011) Journal of Solid-State Circuits
    • Dighe, S.1
  • 13
    • 75649093754 scopus 로고    scopus 로고
    • Near-threshold computing: Reclaiming moore's law through energy efficient integrated circuits
    • February
    • R. G. Dreslinski et al., "Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits," Proceedings of the IEEE, February 2010.
    • (2010) Proceedings of the IEEE
    • Dreslinski, R.G.1
  • 14
    • 0031342511 scopus 로고    scopus 로고
    • The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits
    • December
    • M. Eisele et al., "The Impact of Intra-die Device Parameter Variations on Path Delays and on the Design for Yield of Low Voltage Digital Circuits," IEEE Transactions on VLSI Systems, December 1997.
    • (1997) IEEE Transactions on VLSI Systems
    • Eisele, M.1
  • 15
    • 84880284477 scopus 로고    scopus 로고
    • Cost-effective power delivery for supporting per-core voltage domains for power-constrained processors
    • June
    • H. A. Ghasemi et al., "Cost-Effective Power Delivery for Supporting Per-Core Voltage Domains for Power-Constrained Processors," in Design Automation Conference, June 2012.
    • (2012) Design Automation Conference
    • Ghasemi, H.A.1
  • 16
    • 34247854042 scopus 로고    scopus 로고
    • Scaling, power, and the future of CMOS
    • December
    • M. Horowitz et al., "Scaling, Power, and the Future of CMOS," in Intl. Electron Devices Meeting, December 2005.
    • (2005) Intl. Electron Devices Meeting
    • Horowitz, M.1
  • 17
    • 34548859786 scopus 로고    scopus 로고
    • Comparison of split-versus connected-core supplies in the POWER6 microprocessor
    • February
    • N. James et al., "Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor," in Intl. Solid-State Circuits Conference, February 2007.
    • (2007) Intl. Solid-State Circuits Conference
    • James, N.1
  • 18
    • 84866660547 scopus 로고    scopus 로고
    • VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages
    • June
    • U. R. Karpuzcu et al., "VARIUS-NTV: A Microarchitectural Model to Capture the Increased Sensitivity of Manycores to Process Variations at Near-Threshold Voltages," in Intl. Conference on Dependable Systems and Networks, June 2012.
    • (2012) Intl. Conference on Dependable Systems and Networks
    • Karpuzcu, U.R.1
  • 19
    • 57749178620 scopus 로고    scopus 로고
    • System level analysis of fast, per-core DVFS using on-chip switching regulators
    • February
    • W. Kim et al., "System Level Analysis of Fast, Per-core DVFS Using On-chip Switching Regulators," in Intl. Symposium on High Performance Computer Architecture, February 2008.
    • (2008) Intl. Symposium on High Performance Computer Architecture
    • Kim, W.1
  • 20
    • 79955717091 scopus 로고    scopus 로고
    • A fully-integrated 3-Level DC/DC converter for nanosecondscale DVS with fast shunt regulation
    • February
    • W. Kim et al., "A Fully-integrated 3-Level DC/DC Converter for Nanosecondscale DVS with Fast Shunt Regulation," in Intl. Solid-State Circuits Conference, February 2011.
    • (2011) Intl. Solid-State Circuits Conference
    • Kim, W.1
  • 21
    • 70449730913 scopus 로고    scopus 로고
    • Optimizing total power of many-core processors considering voltage scaling limit and process variations
    • March
    • J. Lee and N. S. Kim, "Optimizing Total Power of Many-core Processors Considering Voltage Scaling Limit and Process Variations," in Intl. Symposium on Low Power Electronics and Design, March 2009.
    • (2009) Intl. Symposium on Low Power Electronics and Design
    • Lee, J.1    Kim, N.S.2
  • 22
    • 84863541593 scopus 로고    scopus 로고
    • McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures
    • December
    • S. Li et al., "McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures," in Intl. Symposium on Microarchitecture, December 2009.
    • (2009) Intl. Symposium on Microarchitecture
    • Li, S.1
  • 23
    • 75649141765 scopus 로고    scopus 로고
    • Ultralow-power design in near-threshold region
    • February
    • D. Markovic et al., "Ultralow-Power Design in Near-Threshold Region," Proceedings of the IEEE, February 2010.
    • (2010) Proceedings of the IEEE
    • Markovic, D.1
  • 24
    • 84860352303 scopus 로고    scopus 로고
    • Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in lowvoltage chips
    • February
    • T. Miller et al., "Booster: Reactive Core Acceleration for Mitigating the Effects of Process Variation and Application Imbalance in Lowvoltage Chips," in Intl. Symposium on High Performance Computer Architecture, February 2012.
    • (2012) Intl. Symposium on High Performance Computer Architecture
    • Miller, T.1
  • 25
    • 29144526605 scopus 로고    scopus 로고
    • Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS
    • December
    • S. Mukhopadhyay et al., "Modeling of Failure Probability and Statistical Design of SRAM Array for Yield Enhancement in Nanoscaled CMOS," Transactions on Computer-Aided Design of Integrated Circuits and Systems, December 2005.
    • (2005) Transactions on Computer-Aided Design of Integrated Circuits and Systems
    • Mukhopadhyay, S.1
  • 27
    • 77957943842 scopus 로고    scopus 로고
    • Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors
    • August
    • J. Park et al., "Accurate Modeling and Calculation of Delay and Energy Overheads of Dynamic Voltage Scaling in Modern High-Performance Microprocessors," Symposium on Low-Power Electronics and Design, August 2010.
    • (2010) Symposium on Low-Power Electronics and Design
    • Park, J.1
  • 28
    • 79955905510 scopus 로고    scopus 로고
    • Achieving uniform performance and maximizing throughput in the presence of heterogeneity
    • February
    • K. Rangan et al., "Achieving Uniform Performance and Maximizing Throughput in the Presence of Heterogeneity," in Intl. Symposium on High Performance Computer Architecture, February 2011.
    • (2011) Intl. Symposium on High Performance Computer Architecture
    • Rangan, K.1
  • 29
    • 33644879118 scopus 로고    scopus 로고
    • January
    • J. Renau et al., "SESC Simulator," January 2005, http://sesc.sourceforge.net.
    • (2005) SESC Simulator
    • Renau, J.1
  • 30
    • 84866720818 scopus 로고    scopus 로고
    • Multiple clock and voltage domains for chip multiprocessors
    • December
    • E. Rotem et al., "Multiple Clock and Voltage Domains for Chip Multiprocessors," in Intl. Symposium on Microarchitecture, December 2009.
    • (2009) Intl. Symposium on Microarchitecture
    • Rotem, E.1
  • 31
    • 38949186007 scopus 로고    scopus 로고
    • VARIUS: A model of process variation and resulting timing errors formicroarchitects
    • February
    • S. Sarangi et al., "VARIUS: A Model of Process Variation and Resulting Timing Errors forMicroarchitects," Transactions on Semiconductor Manufacturing, February 2008.
    • (2008) Transactions on Semiconductor Manufacturing
    • Sarangi, S.1
  • 32
    • 78650879028 scopus 로고    scopus 로고
    • A 40 nm 16-Core 128-thread SPARC SoC processor
    • J. L. Shin et al., "A 40 nm 16-Core 128-Thread SPARC SoC Processor," Journal of Solid-State Circuits, vol. 46, no. 1, 2011.
    • (2011) Journal of Solid-State Circuits , vol.46 , Issue.1
    • Shin, J.L.1
  • 34
    • 52649107085 scopus 로고    scopus 로고
    • Variation-aware application scheduling and power management for chip multiprocessors
    • June
    • R. Teodorescu and J. Torrellas, "Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors," in Intl. Symposium on Computer Architecture, June 2008.
    • (2008) Intl. Symposium on Computer Architecture
    • Teodorescu, R.1    Torrellas, J.2
  • 35
    • 84880309067 scopus 로고    scopus 로고
    • The R Project for Statistical Computing
    • The R Project for Statistical Computing:, http://www.r-project.org/.
  • 36
    • 78149278347 scopus 로고    scopus 로고
    • Scalable thread scheduling and global power management for heterogeneous many-core architectures
    • September
    • J. A. Winter et al., "Scalable Thread Scheduling and Global Power Management for Heterogeneous Many-core Architectures," in Intl. Conference on Parallel Architectures and Compilation Techniques, September 2010.
    • (2010) Intl. Conference on Parallel Architectures and Compilation Techniques
    • Winter, J.A.1
  • 37
    • 84860347210 scopus 로고    scopus 로고
    • AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture
    • February
    • G. Yan et al., "AgileRegulator: A Hybrid Voltage Regulator Scheme Redeeming Dark Silicon for Power Efficiency in a Multicore Architecture," in Intl. Symposium on High Performance Computer Architecture, February 2012.
    • (2012) Intl. Symposium on High Performance Computer Architecture
    • Yan, G.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.