Scalable thread scheduling and global power management for heterogeneous many-core architectures

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2010, Pages 29-39

  Winter, Jonathan A ^a   Albonesi, David H ^b   Shoemaker, Christine A ^c  

^a GOOGLE INC   (United States)

^b Cornell University ^*  (United States)

^c Department of Obstetrics Gynecology   (United States)

Author keywords

computational complexity; global power management; hard errors; heterogeneous chip multiprocessors; many core architectures; process variations; scalability; thread scheduling

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTATIONAL EFFICIENCY; EFFICIENCY; LINEAR PROGRAMMING; PARALLEL ARCHITECTURES; POWER MANAGEMENT; SCALABILITY;

HARD ERRORS; HETEROGENEOUS CHIP MULTIPROCESSOR; MANY-CORE ARCHITECTURE; PROCESS VARIATION; THREAD SCHEDULING;

SCHEDULING;

EID: 78149278347     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1854273.1854283     Document Type: Conference Paper

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