Optimizing total power of many-core processors considering voltage scaling limit and process variations

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2009, Pages 201-206

  Lee, Jungseob ^a   Kim, Nam Sung ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

Many core processor; Parallel applications; Process variations; Voltage and frequency scaling

Indexed keywords

DATA-INTENSIVE APPLICATION; FREQUENCY-SCALING; HIGH THROUGHPUT; LOW SUPPLY VOLTAGES; MANY-CORE; MEMORY FAILURES; OPTIMAL POWER; PARALLEL APPLICATION; PHYSICS SIMULATION; POWER CONSUMPTION; POWER REDUCTIONS; PROCESS VARIATION; SILICON AREA; SUPPLY VOLTAGES; SUPPLY-VOLTAGE SCALING; TOTAL POWER; VOLTAGE-SCALING; WITHIN DIES;

COST REDUCTION; DIES; ELECTRIC POWER UTILIZATION; LOW POWER ELECTRONICS; OPTIMIZATION; POWER ELECTRONICS;

THREE DIMENSIONAL COMPUTER GRAPHICS;

EID: 70449730913     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1594233.1594283     Document Type: Conference Paper

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