Accelerating write by exploiting PCM asymmetries

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2013, Pages 282-293

  Yue, Jianhui ^a   Zhu, Yifeng ^a  

^a UNIVERSITY OF MAINE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODING SCHEME; ELECTRICAL CURRENT; LATENCY REDUCTION; MEMORY LATENCIES; MULTI-CORE PROCESSOR; PERFORMANCE IMPROVEMENTS; POWER CONSTRAINTS;

COMPUTER ARCHITECTURE;

SUPERCOMPUTERS;

EID: 84880277126     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2013.6522326     Document Type: Conference Paper

References (30)

1. K. Bergman, S. Borkar. D. CampbeU, and etc, "ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems Peter Kogge, Editor & Study Lead," 2008.
2. International Technology Roadmap for Semiconductors, 2009.
3. B. C. Lee, E. Ipek, O. Mutlu, and D. Burger, " Architecting Phase Change Memory as a Scalable DRAM Alternative," in Proeeedings of the 36th Annual International Symposium on Computer Arehiteeture, 2009, pp. 2-13.
4. H. Zheng and Z. Zhu, "Power and Performance Trade-Offs in Contemporary DRAM System Designs for Multicore Processors," Computers, IEEE Transactions on, vol. 59, no. 8, pp. 1033-1046, Aug. 2010.
5. S. Thoziyoor, J. H. Ahn, M. Monchiero, J. B. Brockman, and N. P. Jouppi, " A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies," in Proeeedings of the 35th Annual International Symposium on Computer Architecture, 2008, pp. 51-62.
6. P. Zhou, B. Zhao, J. Yang, and Y. Zhang, "A Durable and Energy Efficient Main Memory Using Phase Change Memory Technology," in Proceedings of the 36th Annual International Symposium on Computer Architecture, 2009, pp. 14-23.
7. M. Qureshi, J. Karidis, M. Franceschini, V. Srinivasan, L. Lastras, and B. Abali, "Enhancing Lifetime and Security of PCM-Based Main Memory with Start-Gap Wear Leveling," in Proceedings of the 42nd Annual IEEEIA CM International Symposium on Microarchitecture, 2009, pp. 14-23.
8. E. Ipek, 1. Condit, E. B. Nightingale, D. Burger, and T. Moscibroda, "Dynamically Replicated Memory: Building Reliable Systems from Nanoscale Resistive Memories," in Proceedings of the fifteenth edition of ASPLOS on Architectural Support for Programming Languages and Operating Systems, 2010, pp. 3-14.
9. S. Schechter, G. H. Loh, K Straus, and D. Burger, "Use ECP, not ECC, for Hard Failures in Resistive Memories," in Proceedings of the 37th Annual International Symposium on Computer Architecture, 2010, pp. 141-152.
10. N. H. Seong, D. H. Woo, V. Srinivasan, J. A. Rivers, and H.-H. S. Lee, "SAFER: Stuck-At-Fault Error Recovery for Memories," in Proceedings of the 43rd Annual IEEEIA CM International Symposium on Microarchitecture, 2010, pp. 115-124.
11. D. H. Yoon, N. Muralimanohar, J. Chang, P. Ranganathan, N. P. Jouppi, and M. Erez, "FREE-p: Protecting Non-Volatile Memory against both Hard and Soft Errors," in Proeeedings of the 1 7th International Conference on High-Petformance Computer Architecture, 2011, pp. 466-477.
12. S. Cho and H. Lee, "Flip-N-Write: A Simple Deterministic Technique to Improve PRAM Write Performance, Energy and Endurance," in Proeeedings of the 42nd Annual IEEEIACM International Symposium on Microarchitecture, 2009, pp. 347-357.
13. S. Kang, W. Y. Cho, and etc, "A O.I-/.Lm 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous BurstRead Operation," Solid-State Circuits, IEEE Journal of, vol. 42, no. I , pp. 210-218, Jan. 2007.
14. S. Hanzawa, N. Kitai, and etc, "A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100/.LA Cell Write Current," in IEEE International Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technieal Papers. , 2007, pp. 474-616.
15. K-J. Lee, B.-H. Cho, and etc, "A 90 nm 1. 8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput," Solid-State Circuits, IEEE Journal of, vol. 43, no. I , pp. 150-162, Jan. 2008.
16. R. Kalla, B. Sinharoy, W. J. Starke, and M. Floyd, "Power7: IBM's Next-Generation Server Processor," IEEE Micro, vol. 30, no. 2, pp. 7-15, Mar. 2010.
17. J. Warnock, Y. Chan, W. Huott, and etc, "A 5.2GHz Microprocessor Chip for the IBM zEnterpriseSystem,'' in IEEE International SolidState Cireuits Conferenee, 201 1 . ISSCC 201 1 . Digest of Teehnieal Papers. , 2011, pp. 70-72.
18. S. Ahn, Y. Song, and etc, "Highly Manufacturable High Density Phase Change Memory of 64Mb and Beyond," in Eleetron Devices Meeting, 2004. IEDM Teclmical Digest. IEEE International, Dec. 2004, pp. 907-910.
19. F. Bedeschi, C. Resta, O. Khouri, and etc, "An 8Mb Demonstrator for High-Density 1. 8V Phase-Change Memories," in VLSI Circuits, 2004. Digest of Teehnieal Papers. 2004 Symposium on, June 2004, pp. 442-445.
20. H.-R. Oh, B.-H. Cho, W. Y. Cho, and etc, "Enhanced Write Performance of a 64-Mb Phase-Change Random Access Memory," Solid-State Circuits, IEEE Journal of, vol. 41, no. 1, pp. 122-126, Jan. 2006.
21. S. Kang, W. Cho, K-J. Lee, and etc, "A O.l/.Lm 1.8V 256Mb 66MHz Synchronous Burst PRAM," in Solid-State Cireuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International, Feb. 2006, pp. 487-496.
22. T. Vogel sang, "Understanding the Energy Consumption of Dynamic Random Access Memories," in Proceedings of the 42nd Annual IEEEIACM International Symposium on Microarchiteeture, 2010, pp. 363-374.
23. N. L. Binkert, R. G. Dreslinski, L. R. Hsu, K. T. Lim, A. G. Saidi, and S. K. Reinhardt, "The M5 Simulator: Modeling Networked Systems," IEEE Micro, vol. 26, no. 4, pp. 52-60, 2006.
24. D. Wang, B. Ganesh, N. Tuaycharoen, K. Baynes, A. Jaleel, and B. Jacob, "DRAMsim: A Memory System Simulator;' SIGARCH Comput. Archit. News, vol. 33, no. 4, pp. 100-107, 2005.
25. M. F. Moinuddin K Qureshi and L. Lastras, " lmproving Read Performance of Phase Change Memories via Write Cancellation and Write Pausing," in Proceedings of the 1 6th International Conference on HighPerformance Computer Arehitecture, 2010, pp. 1-11.
26. A. Glew. , "MLP yes! ILP no! In Wild and Crazy ldeas Session," in Proceeding of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, 1998.
27. O. Mutlu and T. Moscibroda, "Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems," in Proeeedings of the 35th Annual International Symposium on Computer Architecture, 2008, pp. 63-74.
28. L. Jiang, B. Zhao, Y. Zhang, 1. Yang, and B. Childers, "lmproving Write Operations in MLC Phase Change Memory," in Proeeedings of the 18th International Conference on High-Petformance Computer Architecture, 2012, pp. 201-210.
29. M. Qureshi, M. Franceschini, A. Jagmohan, and L. Lastras, "PreSET: Improving Performance of Phase Change Memories by Exploiting Asymmetry in Write Times," in Proeeedings of the 39th Annual International Symposium on Computer Arehiteeture, 2012, pp. 380-391.
30. A. Hay, K. Strauss, T. Sherwood, G. H. Loh, and D. Burger, "Preventing PCM Banks from Seizing Too Much Power," in Proceedings of the 44th AnnuaI IEEE/ACM International Symposium on Microarchitecture, 2011, pp. 186-195.