PreSET: Improving performance of phase change memories by exploiting asymmetry in write times

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2012, Pages 380-391

  Qureshi, Moinuddin K ^a   Franceschini, Michele M ^b   Jagmohan, Ashish ^b   Lastras, Luis A ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CANCELLATION TECHNIQUES; FUNDAMENTAL PROPERTIES; IMPROVING PERFORMANCE; MAIN MEMORY; MEMORY CELL; PCM SYSTEMS; PERFORMANCE DEGRADATION; SET OPERATION; STATIC AND DYNAMIC; STORAGE OVERHEAD; WRITE OPERATIONS;

COMPUTER ARCHITECTURE; DEGRADATION; PHASE CHANGE MEMORY;

CACHE MEMORY;

EID: 84864832526     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2012.6237033     Document Type: Conference Paper

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