Power and performance trade-offs in contemporary DRAM system designs for multicore processors

IEEE Transactions on Computers

Volumn 59, Issue 8, 2010, Pages 1033-1046

  Zheng, Hongzhong ^a   Zhu, Zhichun ^a  

^a 1120 Science and Engineering Offices   (United States)

Author keywords

DRAM systems; Multicore processors; performance.; power

Indexed keywords

BURST LENGTH; DEVICE CONFIGURATIONS; DRAM MEMORIES; DRAM TECHNOLOGY; HYBRID CONFIGURATIONS; MULTI-CORE PROCESSOR; MULTI-CORE SYSTEMS; OPTIMAL CHOICE; PERFORMANCE TRADE-OFF; POWER BREAKDOWNS; POWER CONSUMPTION; POWER MODES; POWER PROFILE; POWER SAVINGS; PROCESSOR DESIGN; PROCESSOR POWER CONSUMPTION; RE-CONFIGURABLE; SYSTEM CONFIGURATIONS; SYSTEM DESIGN;

DESIGN; NANOTECHNOLOGY;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 77954159201     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2010.108     Document Type: Article

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