Architecture and design flow for a highly efficient structured ASIC

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 21, Issue 3, 2013, Pages 424-433

  Ho, Man Ho ^a   Ai, Yan Qing ^a   Chau, Thomas Chun Pong ^b   Yuen, Steve C L ^c   Choy, Chiu Sing ^a   Leong, Philip H W ^d   Pun, Kong Pang ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^b IMPERIAL COLLEGE LONDON   (United Kingdom)

^c Electrical and Mechanical Services Department   (Hong Kong)

^d UNIVERSITY OF SYDNEY   (Australia)

Author keywords

Application specific integrated circuit (ASIC); area delay comparison; field programmable gate array (FPGA); structured ASIC (sASIC); via programmable

Indexed keywords

AREA-DELAY COMPARISON; BENCHMARK CIRCUIT; COMPATIBLE DESIGN; DESIGN FLOWS; FABRICATION PROCESS; FUNCTIONAL TEST; LOOK UP TABLE; MIXED MODE; STANDARD-CELL; STRUCTURED APPLICATION SPECIFIC INTEGRATED CIRCUITS; STRUCTURED ASICS; STRUCTURED-ASIC (SASIC); UNIVERSAL MACHINES; VIA-PROGRAMMABLE;

DESIGN; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 84874660054     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2012.2190478     Document Type: Article

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