A highly compatible architecture design for optimum FPGA to structured-ASIC migration

IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE

Volumn , Issue , 2006, Pages 506-510

  Phoon, Hee Kong ^a   Yap, Matthew ^a   Chai, Chuan Khye ^a  

^a Altera Corporation Malaysia   (Malaysia)

Author keywords

[No Author keywords available]

Indexed keywords

CHARACTERIZATION; COMPUTATIONAL METHODS; COMPUTER AIDED DESIGN; INTEGRATED CIRCUIT LAYOUT; VERIFICATION;

ARCHITECTURE DESIGN; ASIC DESIGN; H CELL MAPPING; MIGRATION PATHS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 35148860740     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SMELEC.2006.381114     Document Type: Conference Paper

References (5)

1. R. Camposano, "Will the ASIC Survive", Keynote Address at SBCCI 2004, p5.
2. El-Gamal, J. Cohn, A. Kahng, I. Bolsens, A. Broom, C. Hamlin, P. Magarshack, Z. Or-Bach and L. Pileggi, "Fast, Cheap and Under Control: The Next Implementation Fabric", in Proc. DAC 2003, pp. 354-355.
3. M. Hutton et.al., "Improving FPGA Performance and Area Using an Adaptive Logic Module", in Proc. FPL 2004, pp. 135-144.
4. D. Lewis et.al, "The Stratix II Logic and Routing Architecture", in Proc. FPGA 2005, pp. 14-20.
5. Fabio SOMENZI, "Binary Decision Diagrams", Department of Electrical and Computer Engineering, University of Colorado at Boulder.