Designing via-configurable logic blocks for regular fabric

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 1, 2006, Pages 1-14

  Ran, Yajun ^b   Marek Sadowska, Malgorzata ^a,c  

^a IEEE   (United States)

^b Clear Shape Technologies Inc   (United States)

^c Santa Barbara   (United States)

Author keywords

Fabric; Gate arrays; Regularity; Structured ASICs; Via configurable

Indexed keywords

FABRIC; GATE ARRAYS; REGULARITY; STRUCTURED-ASICS; VIA-CONFIGURABLE;

ARRAYS; CMOS INTEGRATED CIRCUITS; ELECTRIC INVERTERS; ELECTRIC POWER UTILIZATION; TRANSISTORS;

LOGIC CIRCUITS;

EID: 33644967146     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.863196     Document Type: Article

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