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Volumn , Issue , 2004, Pages 590-594

A METAL and VIA maskset programmable VLSI design methodology using PLAs

Author keywords

[No Author keywords available]

Indexed keywords

LITHOGRAPHY MASKS; METAL LAYERS; SEQUENTIAL DESIGNS; VLSI DESIGN;

EID: 16244413620     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (35)

References (21)
  • 1
    • 84860105012 scopus 로고    scopus 로고
    • "Sematech Annual Report." http://www.sematech.org/public/ corporate/annrpt/annrpt02/pdf/mask.pdf, 2002.
    • (2002)
  • 3
    • 84860105015 scopus 로고    scopus 로고
    • E. Design,"http://www.eedesign.com/story/oeg20021206s0034."
  • 5
    • 34547208198 scopus 로고    scopus 로고
    • A VLSI design methodology using i network of PLAs embedded in a regular layout fabric
    • Electronics Research Laboratory, University of California, Berkeley, May
    • S. Khatri, R. Brayton, and A. Sangiovanni-Vincentelli, "A VLSI design methodology using i network of PLAs embedded in a regular layout fabric," Tech. Rep. UCB/ERL M99/50, Electronics Research Laboratory, University of California, Berkeley, May 1999.
    • (1999) Tech. Rep. , vol.UCB-ERL M99-50
    • Khatri, S.1    Brayton, R.2    Sangiovanni-Vincentelli, A.3
  • 16
    • 84888920622 scopus 로고    scopus 로고
    • "BSIM3 Homepage." http://www-davice.eecs.barkeley.edu/~bsim3/ intro.html.
    • BSIM3 Homepage
  • 19
    • 0006996546 scopus 로고    scopus 로고
    • Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA, Nov
    • Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA, Envisia Silicon Ensemble Place-and-route Reference, Nov 1999.
    • (1999) Envisia Silicon Ensemble Place-and-route Reference


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.