Using structured ASIC to improve design productivity

ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings

Volumn , Issue , 2009, Pages 25-28

  Tsai, Yu Wen ^a   Wu, Kun Chen ^a   Tung, Hui Hsiang ^b   Lin, Rung Bin ^b  

^a FARADAY TECHNOLOGY CORPORATION   (Taiwan)

^b YUAN ZE UNIVERSITY   (Taiwan)

Author keywords

NRE; Structured ASIC; TAT

Indexed keywords

DESIGN PRODUCTIVITY; FARADAY TECHNOLOGIES; NON RECURRING ENGINEERING; SOC SOLUTIONS; STRUCTURED ASICS; VERY DEEP SUB MICRONS;

DESIGN; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUITS; PRODUCTIVITY; TECHNOLOGY;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 77950381752     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Faraday Structured ASIC Technology WWW site: http://www.faraday-tech.com/ html/products/structuredASIC.html
2. Cadence SocEncounter User's Guide and Document Reference Manual. 2008.
3. Synopsys Design Compiler User's Guide and Document Reference Manual.2008.
4. Mentor Graphics Calibre User's Guide and Document Reference Manual 2008.
5. Kun-Chen Wu and Yu-Wen Tsai, "Structured ASIC: A Revolution or an Evolution," in Proc. International Symposium on Physical Design, pp. 103-106, 2004.