A structured ASIC design approach using pass transistor logic

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 1787-1790

  Gulati, Kanupriya ^a   Jayakumar, Nikhil ^a   Khatri, Sunil P ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY DECISION DIAGRAMS; COMBINATORIAL CIRCUITS; INTEGRATED CIRCUIT LAYOUT; SEQUENTIAL CIRCUITS; TRANSISTORS;

COMBINATIONAL DESIGNS; DESIGN METHODOLOGY; IF-THEN-ELSE (ITE) CELLS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 34548856006     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378019     Document Type: Conference Paper

References (16)

1. "Sematech Annual Report." http://www.sematech.org/public/ corporateannrpt/annrpt02/pdf/mask.pdf, 2002.
2. A. Sangiovanni-Vincentelli, "The tides of EDA." Keynote Talk, Design Automation Conference, June 2003.
3. A. Koorapaty, V. Chandra, K. Y. TONG, C. Patel, L. Pillegi, and H. Schmit, "Heterogeneous programmable logic block architectures," in Design Automation and Test in Europe Conference, Mar 2003.
4. A. Koorapaty, L. Pillegi, and H. Schmit, "Heterogeneous logic block architectures for via-patterned programmable fabrics," in 13th International Conference on Field Programmable Logic and Applications, Sep 2003.
5. A. Koorapaty, V. Kheterapal, P. Gopalakrishnan, and L. Pillegi, "Exploring logic block granularity for regular fabrics," in Design Automation and Test in Europe Conference, vol. 1, pp. 468-473, Feb 2004.
6. N. Jayakumar and S. Khatri, "A metal and via maskset programmable VLSI design methodology using PLAs," in Proceedings, IEEE/ACM International Conference on Computer-Aided Design, pp. 590-594, Nov 2004.
7. A. Narayan, J. Jain, M. Fujita, and A. Sangiovanni-Vincentelli, "Partitioned ROBDDs-a compact, canonical and efficiently manipulate representation for boolean functions," in Proceedings, IEEE/ACM International Conference on Computer-Aided Design, pp. 547-554, Nov 1996.
8. A. Narayan, A. J. Isles, J. Jain, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Reachability analysis using partirioned-ROBDDs, " in Proceedings, IEEE/ACM International Conference on Computer-Aided Design, pp. 388-393, Nov 1997.
9. "Graphviz - graph visualization software." http://www.graphviz. org.
10. "A method for drawing directed graphs- dot's algorithm." http://www.graphviz.org/Documentation/TSE93.pdf.
11. Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95.134, USA, Envista Silicon Ensemble Place-and-route Reference, Nov 1999.
12. R. Drechsler and J. S. G. Fey, "Synthesis of fully testable circuits from BDDs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, pp. 440-443, March 2004.
13. The VIS Group, "VIS: a system for verification and synthesis." Proceedings of the 8th International Conference on Computer Aided Verification, p428-432, Springer Lecture Notes in Computer Science, #1102, Edited by R. Alur and T. Henzinger, New Brunswick, NJ, July 1996.
14. Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," in Proc. of IEEE Custom Integrated Circuit Conference, pp. 201-204, Jun 2000. http://www-device.eecs.berkeley.edu/ptm.
15. P. McGeer, A. Saldanha, R. Brayton, and A. Sangiovanni-Vincentelli, Logic Synthesis and Optimization, ch. Delay Models and Exact Timing Analysis, pp. 167-189. Kluwer Academic Publishers, 1993.
16. E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. L. Sangiovanni- Vincentelli, "SIS: A System for Sequential Circuit Synthesis," Tech. Rep. UCB/ERL M92/41, Electronics Research Laboratory, Univ. of California, Berkeley, CA 94720, May 1992.