-
7
-
-
0025532128
-
Chortle: A technology mapping program for lookup table-based field programmable gate arrays
-
R. J. Francis, J. Rose, and K. Chung. Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays. In Proceedings of the Design Automation Conference, pages 613-619, 1990.
-
(1990)
Proceedings of the Design Automation Conference
, pp. 613-619
-
-
Francis, R.J.1
Rose, J.2
Chung, K.3
-
8
-
-
0016943409
-
An efficient implementation of edmonds' algorithm for maximum matching on graphs
-
H. N. Gabow. An Efficient Implementation of Edmonds' Algorithm for Maximum Matching on Graphs. Journal of the ACM, 23:221-234, 1976.
-
(1976)
Journal of the ACM
, vol.23
, pp. 221-234
-
-
Gabow, H.N.1
-
9
-
-
0032678594
-
A novel VLSI layout fabric for deep sub-micron applications
-
IEEE/ACM
-
S. Khatri, A. Mehrotra, R. Brayton, A. Sangiovanni-Vincentelli, and R. Otten. A Novel VLSI Layout Fabric For Deep Sub-Micron Applications. In Proceedings of the Design Automation Conference, pages 491-496. IEEE/ACM, 1999.
-
(1999)
Proceedings of the Design Automation Conference
, pp. 491-496
-
-
Khatri, S.1
Mehrotra, A.2
Brayton, R.3
Sangiovanni-Vincentelli, A.4
Otten, R.5
-
11
-
-
0034825930
-
A hardware/software solution for embeddable FPGA
-
F. Lien, J. Feng, E. Huang, C. Sun, T. Liu, N. Liao, and D. Hightower. A Hardware/Software Solution for Embeddable FPGA. In Proceedings of the Custom Integrated Circuits Conference, pages 5.3.1-5.3.4, 2001.
-
(2001)
Proceedings of the Custom Integrated Circuits Conference
-
-
Lien, F.1
Feng, J.2
Huang, E.3
Sun, C.4
Liu, T.5
Liao, N.6
Hightower, D.7
-
14
-
-
84896693795
-
Implementation of O (nm log n) weighted matchings in general graphs. the power of data structures
-
K. Mehlhorn and G. Schafer. Implementation of O (nm log n) Weighted Matchings in General Graphs. The Power of Data Structures. In Algorithm Engineering, pages 23-38, 2000.
-
(2000)
Algorithm Engineering
, pp. 23-38
-
-
Mehlhorn, K.1
Schafer, G.2
-
16
-
-
0025536718
-
Logic synthesis for programmable gate arrays
-
R. Murgai, N. Nishizaki, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli. Logic Synthesis for Programmable Gate Arrays. In Proceedings of the Design Automation Conference, pages 620-625, 1990.
-
(1990)
Proceedings of the Design Automation Conference
, pp. 620-625
-
-
Murgai, R.1
Nishizaki, N.2
Shenoy, N.3
Brayton, R.K.4
Sangiovanni-Vincentelli, A.5
-
17
-
-
84862419707
-
-
World Wide Web
-
Opencores. IP Cores Repsoitory. World Wide Web, http://www.opencore.com.
-
IP Cores Repsoitory
-
-
-
18
-
-
4444297526
-
-
Customizable and programmable cell array, U.S. Patent 6,331,790, Issued 18 Dec.
-
Z. Or-Bach, Z. Wurman, R. Zeman, and L. Cooke. Customizable and programmable cell array, U.S. Patent 6,331,790, Issued 18 Dec. 2001.
-
(2001)
-
-
Or-Bach, Z.1
Wurman, Z.2
Zeman, R.3
Cooke, L.4
-
19
-
-
0038040153
-
An architectural exploration of via patterned gate arrays
-
C. Patel, A. Cozzi, H. Schmit, and L. Pileggi. An Architectural Exploration of Via Patterned Gate Arrays. In Proceedings of the International Symposium on Physical Design, pages 184-189, 2003.
-
(2003)
Proceedings of the International Symposium on Physical Design
, pp. 184-189
-
-
Patel, C.1
Cozzi, A.2
Schmit, H.3
Pileggi, L.4
-
20
-
-
0042635594
-
Exploring regular fabrics to optimize the performance-cost trade-off
-
IEEE/ACM
-
L. Pileggi, H. Schmit, A. J. Strojwas, V. Kheterpal, A. Koorapaty, C. Patel, V. Rovner, and K. Y. Tong. Exploring Regular Fabrics to Optimize the Performance-Cost Trade-Off. In Proceedings of the Design Automation Conference, pages 782-787. IEEE/ACM, 2003.
-
(2003)
Proceedings of the Design Automation Conference
, pp. 782-787
-
-
Pileggi, L.1
Schmit, H.2
Strojwas, A.J.3
Kheterpal, V.4
Koorapaty, A.5
Patel, C.6
Rovner, V.7
Tong, K.Y.8
-
21
-
-
0025682809
-
The effect of switch box flexibility on routability of field programmable gate arrays
-
J. Rose and S. Brown. The Effect of Switch Box Flexibility on Routability of Field Programmable Gate Arrays. In Proceedings of the Custom Integrated Circuits Conference, pages 27.5.1-27.5.4, 1990.
-
(1990)
Proceedings of the Custom Integrated Circuits Conference
-
-
Rose, J.1
Brown, S.2
-
23
-
-
0025505369
-
Architecture of field programmable gate arrays: The effect of logic block functionality on area efficiency
-
J. Rose, R. Francis, D. Lewis, and P. Chow. Architecture of Field Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency. In IEEE Journal of Solid-State Circuits, pages 1217-1225, 1990.
-
(1990)
IEEE Journal of Solid-state Circuits
, pp. 1217-1225
-
-
Rose, J.1
Francis, R.2
Lewis, D.3
Chow, P.4
-
27
-
-
0036907308
-
A Hybrid ASIC and FPGA architecture
-
P. S. Zuchowski, C. B. Reynolds, R. J. Grupp, S. G. Davis, B. Cremen, and B. Troxel. A Hybrid ASIC and FPGA Architecture. In Proceedings of the International Conference on Computer-Aided Design, pages 187-194, 2002.
-
(2002)
Proceedings of the International Conference on Computer-aided Design
, pp. 187-194
-
-
Zuchowski, P.S.1
Reynolds, C.B.2
Grupp, R.J.3
Davis, S.G.4
Cremen, B.5
Troxel, B.6
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