Structured logic arrays for future CMOS technologies

Canadian Conference on Electrical and Computer Engineering

Volumn , Issue , 2007, Pages 235-238

  Mehrabadi, Roozbeh ^a   Yuan, Shaohua ^a   Saleh, Resve ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

CAD; PLA delay, power and area; Programable logic arrays; Structured ASIC

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ARSENIC COMPOUNDS; BUILT-IN SELF TEST; COMPUTER AIDED DESIGN; DECISION MAKING; ELECTRIC BATTERIES; ELECTRIC CURRENTS; ELECTRIC POWER SUPPLIES TO APPARATUS; FUZZY LOGIC; INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS; NETWORKS (CIRCUITS); OPTICAL DESIGN; PARAMETER ESTIMATION; PROBLEM SOLVING; STANDARDS; TESTING; TIMING CIRCUITS;

ASIC DESIGNS; BUILT IN SELF TEST (BIST); CAD TOOLS; CAPACITIVE LOADS; CIRCUIT TIMING; CMOS TECHNOLOGIES; CRITICAL PATH DELAYS; DEEP SUB-MICRON (DSM); DESIGN METHODS; ELECTRICAL AND COMPUTER ENGINEERING (ECE); INDEPENDENT PARAMETERS; LOGIC ARCHITECTURES; LOGIC ARRAYS; PROGRAMMABLE LOGIC ARRAY (PLA); SELF REPAIRING; SELF TESTING; STANDARD CELLS;

TECHNOLOGY;

EID: 48749087544     PISSN: 08407789     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CCECE.2007.64     Document Type: Conference Paper

References (9)

1. R. Saleh, G. Lim, T. Kadowaki, K. Uchiyama, "Trends in low power digital system-on-chip designs," Proceedings. International Symposium on Quality Electronic Design, 2002., vol., no.pp. 373- 378, 2002.
2. X. Wang, M. Ottavi, F. Meyer, F. Lombardi, "On the yield of compiler-based eSRAMs," Proceedings. 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. , vol., no.pp. 11-19, 10-13 Oct. 2004.
3. Berkeley PLA Test Set, January 30, 1988; included under espresso-examples directory with the SIS package. (references)
4. S.J.E. Wilton, N. Kafafi, J. Wu, K.A. Bozman, V. Aken'Ova, R. Saleh, "Design Considerations for Soft Embedded Programmable Logic Cores", IEEE Journal of Solid-State Circuits, vol. 40, no. 2, Feb 2005, pp. 485-497.
5. B. Zahiri, "Structured ASICs: Opportunities and Challenges," Proceedings 21st International Conference on Computer Design, Oct. 2003, pp. 404-409.
6. International Technology Roadmap for Semiconductors (ITRS), 2001.
7. D. A. Hodges, H. G. Jackson, R. A. Saleh, Analysis and Design of Digital Integrated Circuits: In Deep Submicron Technology, McGraw Hill, New York 2004, 3rd Ed..
8. J.S. Wang, C. R. Chang, C. Yeh, "Analysis and Design of High-speed and Low-Power CMOS PLA", IEEE J. Solid-State Circuits,, vol. 36, pp.1250-1262, Aug. 2001.
9. Artisan Co. "TSMC 0.18mm Process 1.8-Volt SAGE-X™ Standard Cell Library Data book", September 2003, Release 4.1.