High performance configurable distributed hybrid memory in structured ASIC

IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE

Volumn , Issue , 2008, Pages 27-32

  Oh, Guan Hoe ^a   Lor, Wey Tsen ^a   Phoon, Hee Kong ^a   Lim, Chooi Pei ^a  

^a Altera Corporation Malaysia   (Malaysia)

Author keywords

[No Author keywords available]

Indexed keywords

ASIC DESIGN FLOW; BLOCK MEMORIES; BLOCK RAMS; CONFIGURABLE; CUSTOM DESIGN; DESIGN COMPLEXITY; DISTRIBUTED MEMORY; DISTRIBUTED MEMORY ARCHITECTURE; HYBRID FLOW; HYBRID MEMORIES; IMPLEMENTATION STRATEGIES; LOGIC CELLS; MEMORY APPLICATIONS; MEMORY ARRAY; SMALL SIZE; STRUCTURED ASIC;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN; INTEGRATED CIRCUITS; LOGIC DEVICES; MAGNETIC PROSPECTING; RANDOM ACCESS STORAGE; RESEARCH LABORATORIES;

ELECTRIC POWER SUPPLIES TO APPARATUS;

EID: 65949121150     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SMELEC.2008.4770270     Document Type: Conference Paper

References (5)

1. Kar Keng Chua, "Hybrid Logic Element in Structure ASIC", US Patent 10/884,460.
2. D. Chinnery and K. Keutzer, "Closing the Gap Between ASIC and Custom", Norwell, MA: Kluwer, 2002.
3. Altera Stratix II Design Team, "Altera Stratix II Handbook, TriMatrix Embedded Memory Blocks Chapter", www.altera.com
4. Altera Stratix III Design Team, "Altera Stratix III Handbook, TriMatrix Embedded Memory Blocks Chapter", www.altera.com
5. Hee Kong Phoon, Yap, M. ,Chuan Khye Chai "A Highly Compatible Architecture Design for Optimum FPGA to StructuredASIC migration", ICSE'06 (Pubitemid 47533688)