Exploring logic block granularity for regular fabrics

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 468-473

  Koorapaty, A ^a   Kheterpal, V ^a   Gopalakrishnan, P ^a   Fu, M ^a   Pileggi, L ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EXPLORING LOGIC BLOCK GRANULARITY; LOOK-UP TABLES (LUT); REGULAR FABRICS; GLOBAL ROUTING; LOGIC BLOCK ARCHITECTURE; LOGIC FABRICS; LOGIC FUNCTIONS; PROGRAMMABILITY; STANDARD CELL; VIA-CONFIGURABLE LOGIC BLOCKS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; COMPUTER AIDED MANUFACTURING; ELECTRONICS PACKAGING; FORMAL LOGIC; LOGIC GATES; NANOTECHNOLOGY; SILICON; DESIGN; EXHIBITIONS;

FIELD PROGRAMMABLE GATE ARRAYS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 3042611828     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268890     Document Type: Conference Paper

References (11)

1. http://www.siliconmetrics.com/Products/CR.asp.
2. http://www.mondes.com/products/dolphin.htm.
3. E. Ahmed and J. Rose. The effect of lut and cluster size on deep-submicron fpga performance and density. ACM International Symposium on FPGAs, 2000.
4. V. Betz, J. Rose, and A. Marquardt. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, 1999.
5. J. Cong and Y. Ding. Flowmap: An optimal technology mapping algorithm for delay optimization in lookup-table based fpga designs. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, January 1994.
6. A. Koorapaty. Modular, fabric-specific synthesis and heterogeneous logic block architectures for regular fabrics. Ph.D. Thesis, Center for Silicon System Implementation, Carnegie Mellon University, August 2003.
7. A. Koorapaty, V. Chandra, K. Y. Tong, C. Patel, L. Pileggi, and H. Schmit. Heterogeneous programmable logic block architectures. Proceedings of Design Automation and Test in Europe, March 2003.
8. A. Koorapaty, L. Pileggi, and H. Schmit. Heterogeneous logic block architectures for via-patterned programmable fabrics. 13th International Conference on Field Programmable Logic and Applications, September 2003.
9. L. Pileggi, H. Schmit, J. T. Shah, K. Y. Tong, C. Patel, and V. Chandra. A via patterned gate array (vpga). Technical Report Series, Center for Silicon System Implementation, No. CSSI 02-15, March 2002.
10. L. Pileggi, H. Schmit, A. J. Strojwas, P. Gopalakrishnan, V. Kheterpal, A. Koorapaty, C. Patel, V. Rovner, and K. Y. Tong. Exploring regular fabrics to optimize the performance-cost trade-off. Proceedings of the ACM/IEEE Design Automation Conference (DAC), June 2003.
11. K. Y. Tong, V. Kheterpal, V. Rovner, L. Pileggi, H. Schmit, and R. Puri. Regular logic fabrics for via patterned gate array (vpga). IEEE Custom Integrated Circuits Conference.