A lithography-friendly structured ASIC design approach

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2008, Pages 315-320

  Gopalani, Salman ^a   Khatri, Sunil P ^b   Garg, Rajesh ^b   Cheng, Mosong ^b  

^a NATIONAL INSTRUMENTS   (United States)

^b Texas AandM University   (United States)

Author keywords

ASIC; Lithography; OPC

Indexed keywords

AREA PENALTIES; ASIC; ASIC DESIGNS; BENCHMARK CIRCUITS; CIRCUIT BEHAVIORS; CIRCUIT IMPLEMENTATIONS; CIRCUIT STRUCTURES; DELAY PENALTIES; FEATURE SIZES; LAYOUT STRUCTURES; MANUFACTURING COSTS; MASK COSTS; METAL MASKS; NAND GATES; OPC; OPTICAL PROXIMITY EFFECTS; POLY LAYERS; POWER INCREASES; SIMULATION RESULTS; SYSTEMATIC VARIATIONS; TURN-AROUND;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; DESIGN; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; LAKES; NETWORKS (CIRCUITS); STRUCTURAL DESIGN;

ELECTRIC POWER SUPPLIES TO APPARATUS;

EID: 56749109528     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1366110.1366185     Document Type: Conference Paper

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