Fast SEU detection and correction in LUT configuration bits of sram-based FPGAs

Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM

Volumn , Issue , 2007, Pages

  Zarandi, Hamid R ^a,b   Miremadi, Seyed Ghassem ^a   Argyrides, Costas ^b   Pradhan, Dhiraj K ^b  

^a SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

^b UNIVERSITY OF BRISTOL   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); ERROR CORRECTION; ORBITS; REMOTE SENSING; STATIC RANDOM ACCESS STORAGE;

CLOCK CYCLES; CORRECTION CYCLES;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34548791654     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2007.370378     Document Type: Conference Paper

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