메뉴 건너뛰기




Volumn 59, Issue 12, 2012, Pages 849-852

Guest editorial for the special issue on ultra-low-voltage VLSI circuits and systems for green computing

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER CIRCUITS; TIMING CIRCUITS; VLSI CIRCUITS;

EID: 84873447254     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2012.2231011     Document Type: Review
Times cited : (16)

References (27)
  • 1
    • 84855652495 scopus 로고    scopus 로고
    • Ultra-low power VLSI circuit design demystified and explained: A tutorial
    • Jan
    • M. Alioto, "Ultra-low power VLSI circuit design demystified and explained: A tutorial," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 1, pp. 3-29, Jan. 2012.
    • (2012) IEEE Trans. Circuits Syst. I, Reg. Papers , vol.59 , Issue.1 , pp. 3-29
    • Alioto, M.1
  • 2
    • 75649093754 scopus 로고    scopus 로고
    • Near-threshold computing: Reclaiming Moore's law through energy efficient integrated circuits
    • Feb
    • R. G. Dreslinski, M.Wieckowski, D. Blaauw, D. Sylvester, and T. Mudge, "Near-threshold computing: Reclaiming Moore's law through energy efficient integrated circuits," Proc. IEEE, vol. 98, no. 2, pp. 253-266, Feb. 2010.
    • (2010) Proc. IEEE , vol.98 , Issue.2 , pp. 253-266
    • Dreslinski, R.G.1    Wieckowski, M.2    Blaauw, D.3    Sylvester, D.4    Mudge, T.5
  • 4
    • 80052649741 scopus 로고    scopus 로고
    • The swarm at the edge of the cloud - A new perspective on wireless
    • Honolulu, HI, Jun.
    • J. Rabaey, "The swarm at the edge of the cloud - A new perspective on wireless," in VLSI Symp. Tech. Dig., Honolulu, HI, Jun. 2011, pp. 6-8.
    • (2011) VLSI Symp. Tech. Dig. , pp. 6-8
    • Rabaey, J.1
  • 5
    • 84873417112 scopus 로고    scopus 로고
    • Truths and myths of embedded computing
    • San Diego, CA, Jun.
    • S. Borkar, "Truths and myths of embedded computing," in Proc. 48th DAC, San Diego, CA, Jun. 2011.
    • (2011) Proc. 48th DAC
    • Borkar, S.1
  • 7
    • 84873412102 scopus 로고    scopus 로고
    • Reliable ultra-low voltage cache design for many-core systems
    • Dec
    • M. Zhang, V. Stojanovic, and P. Ampadu, "Reliable ultra-low voltage cache design for many-core systems," IEEE Trans. Circuits Syst. II, vol. 59, no. 12, pp. 858-862, Dec. 2012.
    • (2012) IEEE Trans. Circuits Syst. II , vol.59 , Issue.12 , pp. 858-862
    • Zhang, M.1    Stojanovic, V.2    Ampadu, P.3
  • 9
    • 84873384013 scopus 로고    scopus 로고
    • Sensing margin enhancement techniques for ultra-low voltage SRAMs utilizing bitline boosting current and equalized bitline leakage
    • Dec
    • A. T. Do, Q. N. Truc, and T. T. Kim, "Sensing margin enhancement techniques for ultra-low voltage SRAMs utilizing bitline boosting current and equalized bitline leakage," IEEE Trans. Circuits Syst. II, vol. 59, no. 12, pp. 868-872, Dec. 2012.
    • (2012) IEEE Trans. Circuits Syst. II , vol.59 , Issue.12 , pp. 868-872
    • Do, A.T.1    Truc, Q.N.2    Kim, T.T.3
  • 10
    • 84873412540 scopus 로고    scopus 로고
    • A 40 nm subthreshold 5 T SRAM bit cell with improved read and write stability
    • Dec
    • A. Teman, A. Mordakhay, J. Mezhibovsky, and A. Fish, "A 40 nm subthreshold 5 T SRAM bit cell with improved read and write stability," IEEE Trans. Circuits Syst. II, vol. 59, no. 12, pp. 873-877, Dec. 2012.
    • (2012) IEEE Trans. Circuits Syst. II , vol.59 , Issue.12 , pp. 873-877
    • Teman, A.1    Mordakhay, A.2    Mezhibovsky, J.3    Fish, A.4
  • 11
    • 84873405974 scopus 로고    scopus 로고
    • Variability analysis of sense amplifier for FinFET subthreshold SRAM applications
    • Dec
    • M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, P. Su, and C.-T. Chuang, "Variability analysis of sense amplifier for FinFET subthreshold SRAM applications," IEEE Trans. Circuits Syst. II, vol. 59, no. 12, pp. 878-882, Dec. 2012.
    • (2012) IEEE Trans. Circuits Syst. II , vol.59 , Issue.12 , pp. 878-882
    • Fan, M.-L.1    Hu, V.P.-H.2    Chen, Y.-N.3    Su, P.4    Chuang, C.-T.5
  • 12
    • 84873479663 scopus 로고    scopus 로고
    • Ultra-low voltage split-data aware embedded SRAM for mobile video applications
    • Dec
    • N. Gong, S. Jiang, A. Challapalli, S. Fernandes, and R. Sridhar, "Ultra-low voltage split-data aware embedded SRAM for mobile video applications," IEEE Trans. Circuits Syst. II, vol. 59, no. 12, pp. 883-887, Dec. 2012.
    • (2012) IEEE Trans. Circuits Syst. II , vol.59 , Issue.12 , pp. 883-887
    • Gong, N.1    Jiang, S.2    Challapalli, A.3    Fernandes, S.4    Sridhar, R.5
  • 13
    • 84873413313 scopus 로고    scopus 로고
    • A 0.6-V 800-MHz all-digital phase-locked loop with a digital supply regulator
    • Dec
    • K.-H. Cheng, J.-C. Liu, and H.-Y. Huang, "A 0.6-V 800-MHz all-digital phase-locked loop with a digital supply regulator," IEEE Trans. Circuits Syst. II, vol. 59, no. 12, pp. 888-892, Dec. 2012.
    • (2012) IEEE Trans. Circuits Syst. II , vol.59 , Issue.12 , pp. 888-892
    • Cheng, K.-H.1    Liu, J.-C.2    Huang, H.-Y.3
  • 14
    • 84873417616 scopus 로고    scopus 로고
    • All-digital adaptive clocking to tolerate transient supply noise in low voltage operation
    • Dec 2012
    • K. Chae and S. Mukhopadhyay, "All-digital adaptive clocking to tolerate transient supply noise in low voltage operation," IEEE Trans. Circuits Syst. II, vol. 59, no. 12, pp. 893-897, Dec. 2012.
    • IEEE Trans. Circuits Syst. II , vol.59 , Issue.12 , pp. 893-897
    • Chae, K.1    Mukhopadhyay, S.2
  • 15
    • 84873404853 scopus 로고    scopus 로고
    • Variation-resilient building blocks for ultra-low-energy sub-threshold design
    • Dec
    • N. Reynders and W. Dehaene, "Variation-resilient building blocks for ultra-low-energy sub-threshold design," IEEE Trans. Circuits Syst. II, vol. 59, no. 12, pp. 898-902, Dec. 2012.
    • (2012) IEEE Trans. Circuits Syst. II , vol.59 , Issue.12 , pp. 898-902
    • Reynders, N.1    Dehaene, W.2
  • 16
    • 84873409154 scopus 로고    scopus 로고
    • Wide-range dynamic power management in low-voltage low-power subthreshold SCL
    • Dec
    • A. Tajalli and Y. Leblebici, "Wide-range dynamic power management in low-voltage low-power subthreshold SCL," IEEE Trans. Circuits Syst. II, vol. 59, no. 12, pp. 903-907, Dec. 2012.
    • (2012) IEEE Trans. Circuits Syst. II , vol.59 , Issue.12 , pp. 903-907
    • Tajalli, A.1    Leblebici, Y.2
  • 17
    • 84873405491 scopus 로고    scopus 로고
    • A 4 R/2 W register file design for UDVS microprocessors in 65 nm CMOS
    • Dec
    • P.-Y. Chang, T.-J. Lin, J.-S. Wang, and Y.-H. Yu, "A 4 R/2 W register file design for UDVS microprocessors in 65 nm CMOS," IEEE Trans. Circuits Syst. II, vol. 59, no. 12, pp. 908-912, Dec. 2012.
    • (2012) IEEE Trans. Circuits Syst. II , vol.59 , Issue.12 , pp. 908-912
    • Chang, P.-Y.1    Lin, T.-J.2    Wang, J.-S.3    Yu, Y.-H.4
  • 18
    • 84873410214 scopus 로고    scopus 로고
    • Ultra-low-power error correction circuits - Technology scaling and sub-VT operation
    • Dec
    • C. Winstead and J. Neves Rodrigues, "Ultra-low-power error correction circuits - Technology scaling and sub-VT operation," IEEE Trans. Circuits Syst. II, vol. 59, no. 12, pp. 913-917, Dec. 2012.
    • (2012) IEEE Trans. Circuits Syst. II , vol.59 , Issue.12 , pp. 913-917
    • Winstead, C.1    Neves Rodrigues, J.2
  • 20
    • 84873463559 scopus 로고    scopus 로고
    • Low-power level shifter for multi supply voltage designs
    • Dec
    • M. Lanuzza, P. Corsonello, and S. Perri, "Low-power level shifter for multi supply voltage designs," IEEE Trans. Circuits Syst. II, vol. 59, no. 12, pp. 922-926, Dec. 2012.
    • (2012) IEEE Trans. Circuits Syst. II , vol.59 , Issue.12 , pp. 922-926
    • Lanuzza, M.1    Corsonello, P.2    Perri, S.3
  • 21
    • 84873408154 scopus 로고    scopus 로고
    • Variation-tolerant architecture for ultra low power shared-L1 processor clusters
    • Dec
    • M. Reza Kakoee, I. Loi, and L. Benini, "Variation-tolerant architecture for ultra low power shared-L1 processor clusters," IEEE Trans. Circuits Syst. II, vol. 59, no. 12, pp. 927-931, Dec. 2012.
    • (2012) IEEE Trans. Circuits Syst. II , vol.59 , Issue.12 , pp. 927-931
    • Reza Kakoee, M.1    Loi, I.2    Benini, L.3
  • 22
    • 84873425228 scopus 로고    scopus 로고
    • Ultra-lowvoltage operation of CMOS analog circuits: Amplifiers, oscillators, and rectifiers
    • Dec
    • C. Galup-Montoro, M. C. Schneider, and M. B. Machado, "Ultra-lowvoltage operation of CMOS analog circuits: Amplifiers, oscillators, and rectifiers," IEEE Trans. Circuits Syst. II, vol. 59, no. 12, pp. 932-936, Dec. 2012.
    • (2012) IEEE Trans. Circuits Syst. II , vol.59 , Issue.12 , pp. 932-936
    • Galup-Montoro, C.1    Schneider, M.C.2    MacHado, M.B.3
  • 23
    • 84873405413 scopus 로고    scopus 로고
    • A programmable 34 nW/channel sub-threshold signal band power extractor on a body sensor node SoC
    • Dec
    • A. Klinefelter, Y. Zhang, B. Otis, and B. H. Calhoun, "A programmable 34 nW/channel sub-threshold signal band power extractor on a body sensor node SoC," IEEE Trans. Circuits Syst. II, vol. 59, no. 12, pp. 937- 941, Dec. 2012.
    • (2012) IEEE Trans. Circuits Syst. II , vol.59 , Issue.12 , pp. 937-941
    • Klinefelter, A.1    Zhang, Y.2    Otis, B.3    Calhoun, B.H.4
  • 24
    • 84873405588 scopus 로고    scopus 로고
    • Minimum energy analysis and experimental verification of a latch-based subthreshold FPGA
    • Dec
    • P. J. Grossmann, M. E. Leeser, and M. Onabajo, "Minimum energy analysis and experimental verification of a latch-based subthreshold FPGA," IEEE Trans. Circuits Syst. II, vol. 59, no. 12, pp. 942-946, Dec. 2012.
    • (2012) IEEE Trans. Circuits Syst. II , vol.59 , Issue.12 , pp. 942-946
    • Grossmann, P.J.1    Leeser, M.E.2    Onabajo, M.3
  • 25
    • 84873414650 scopus 로고    scopus 로고
    • A fast ULV logic synthesis flow in many-Vt CMOS processes for minimum energy under timing constraints
    • Dec
    • D. Bol, C. Hocquet, and F. Regazzoni, "A fast ULV logic synthesis flow in many-Vt CMOS processes for minimum energy under timing constraints," IEEE Trans. Circuits Syst. II, vol. 59, no. 12, pp. 947-951, Dec. 2012.
    • (2012) IEEE Trans. Circuits Syst. II , vol.59 , Issue.12 , pp. 947-951
    • Bol, D.1    Hocquet, C.2    Regazzoni, F.3
  • 26
    • 84873404852 scopus 로고    scopus 로고
    • A design methodology for voltage overscaled ultra-low power systems
    • Dec
    • D. Jeon, M. Seok, Z. Zhang, D. Blaauw, and D. Sylvester, "A design methodology for voltage overscaled ultra-low power systems," IEEE Trans. Circuits Syst. II, vol. 59, no. 12, pp. 952-956, Dec. 2012.
    • (2012) IEEE Trans. Circuits Syst. II , vol.59 , Issue.12 , pp. 952-956
    • Jeon, D.1    Seok, M.2    Zhang, Z.3    Blaauw, D.4    Sylvester, D.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.