A 40-nm sub-threshold 5T SRAM bit cell with improved read and write stability

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 59, Issue 12, 2012, Pages 873-877

  Teman, Adam ^a   Mordakhay, Anatoli ^b   Mezhibovsky, Janna ^a   Fish, Alexander ^a  

^a BEN GURION UNIVERSITY OF THE NEGEV   (Israel)

^b BAR ILAN UNIVERSITY   (Israel)

Author keywords

CMOS memory integrated circuits; leakage suppression; SRAM; sub threshold (ST) static random access memory (SRAM); ultra low power

Indexed keywords

CELLS; CMOS INTEGRATED CIRCUITS; CYTOLOGY; LOW POWER ELECTRONICS; THRESHOLD VOLTAGE;

ASYMMETRIC CHARACTERISTIC; CMOS MEMORY INTEGRATED CIRCUITS; INDUSTRY STANDARDS; LEAKAGE SUPPRESSION; LOW SUPPLY VOLTAGES; STATIC POWER REDUCTION; STATIC RANDOM ACCESS MEMORY; ULTRA LOW POWER;

STATIC RANDOM ACCESS STORAGE;

EID: 84873412540     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2012.2231020     Document Type: Article

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