A 4R/2W register file design for UDVS microprocessors in 65-nm CMOS

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 59, Issue 12, 2012, Pages 908-912

  Chang, Pei Yao ^a   Lin, Tay Jyi ^b   Wang, Jinn Shyan ^a   Yu, Yen Hsiang ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

^b CCU ^*  (Taiwan)

Author keywords

Register file design; subthreshold design; ultra wide dynamic voltage scaling (UDVS)

Indexed keywords

CMOS INTEGRATED CIRCUITS; ENERGY EFFICIENCY; VOLTAGE SCALING;

ENERGY EFFICIENT; OPERATING VOLTAGE; REGISTER FILES; STATE OF THE ART; SUB-THRESHOLD DESIGN; SUBTHRESHOLD OPERATION; ULTRA-WIDE; WRITE NOISE MARGINS;

INTEGRATED CIRCUIT DESIGN;

EID: 84873405491     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2012.2231031     Document Type: Article

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