A fast ULV logic synthesis flow in many-Vt CMOS processes for minimum energy under timing constraints

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 59, Issue 12, 2012, Pages 947-951

  Bol, David ^a   Hocquet, Cédric ^b,c   Regazzoni, Francesco ^b,c  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

^b National Instruments   (Belgium)

^c UNIVERSITY OF LUGANO   (Switzerland)

Author keywords

Design automation; digital integrated circuits; timing closure; ultra low power; ultra low voltage

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ENERGY CONSERVATION; INTEGRATED CIRCUIT DESIGN; LOGIC SYNTHESIS; LOW POWER ELECTRONICS;

DESIGN AUTOMATIONS; MINIMUM ENERGY POINT; TARGET FREQUENCIES; TIMING CLOSURES; TIMING CONSTRAINTS; ULTRA LOW POWER; ULTRA-LOW-VOLTAGE; VOLTAGE SELECTION;

TIMING CIRCUITS;

EID: 84873414650     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2012.2231034     Document Type: Article

References (11)

1. B. Calhoun, A. Wang, and A. Chandrakasan, "Modeling and sizing for minimum energy operation in subthreshold circuits," IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1778-1786, Sep. 2005.
2. F. Zhang, Y. Zhang, J. Silver, Y. Shakhsheer, M. Nagaraju, A. Klinefelter, J. Pandey, J. Boley, E. Carlson, A. Shrivastava, B. Otis, and B. Calhoun, "A batteryless 19 μW MICS/ISM-band energy harvesting body area sensor node SoC," in Proc. IEEE Int. Solid-State Circuits Conf., 2012, pp. 298-300.
3. G. Chen, M. Fojtik, D. Kim, D. Fick, J. Park, M. Seok, M.-T. Chen, Z. Foo, D. Sylvester, and D. Blaauw, "Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells," in Proc. IEEE Int. Solid-State Circuits Conf., 2010, pp. 288-289.
4. D. Bol, J. De Vos, C. Hocquet, F. Botman, F. Durvaux, S. Boyd, D. Flandre, and J. Legat, "A 25 MHz 7 μW/MHz ultra-low-voltage microcontroller SoC in 65 nm LP/GP CMOS for low-carbon wireless sensor nodes," in Proc. IEEE Int. Solid-State Circuits Conf., 2012, pp. 490-492.
5. C.-H. Yang, T.-H. Yu, and D. Markovi'c, "Power and area minimization of reconfigurable FFT processors: A 3GPP-LTE example," IEEE J. Solid- State Circuits, vol. 47, no. 3, pp. 757-768, Mar. 2012.
6. D. Bol, "Robust and energy-efficient ultra-low-voltage circuit design under timing constraints in 65/45 nm CMOS," MDPI J. Low-Power Electron. Appl., vol. 1, no. 1, pp. 1-19, Jan. 2011.
7. M. Alioto, "Ultra-low power VLSI circuit design demystified and explained: A tutorial," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 1, pp. 3-29, Jan. 2012.
8. D. Bol, D. Flandre, and J.-D. Legat, "Technology flavor selection and adaptive techniques for timing-constrained 45 nm subthreshold circuits," in Proc. ACM Int. Symp. Low-Power Electron. Des., 2009, pp. 21-26.
9. R. Rithe, S. Chou, J. Gu, A. Wang, S. Datla, G. Gammie, D. Buss, and A. Chandrakasan, "The effect of random dopant fluctuations on logic timing at low voltage," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 5, pp. 911-924, May 2012.
10. F. Arnaud, B. Duriez, B. Tavel, L. Pain, J. Todeschini, M. Jurdit, Y. Laplanche, F. Boeuf, F. Salvetti, D. Lenoble, J. P. Reynard, F. Wacquant, P. Morin, N. Emonet, D. Barge, M. Bidaud, D. Ceccarelli, P. Vannier, Y. Loquet, H. Leninger, F. Judong, C. Perrot, I. Guilmeau, R. Palla, A. Beverina, V. DeJonghe, M. Broekaart, V. Vachellerie, R. A. Bianchi, B. Borot, T. Devoivre, N. Bicais, D. Roy, M. Denais, K. Rochereau, R. Difrenza, N. Planes, H. Brut, L. Vishnobulta, D. Reber, P. Stolk, and M.Woo, "Low cost 65 nm CMOS platform for low power & general purpose applications," in Proc. Symp. VLSI, 2004, pp. 10-11.
11. M. Henry, S. Griffin, and L. Nazhandali, "Fast simulation framework for subthreshold circuits," in Proc. IEEE Int. Conf. Circuits Syst., 2009, pp. 2549-2552.