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Volumn 59, Issue 12, 2012, Pages 918-921
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Large within-die gate delay variations in sub-threshold logic circuits at low temperature
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Author keywords
Delay variations; device matrix array (DMA); sub threshold; temperature
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Indexed keywords
DELAY CIRCUITS;
LOGIC CIRCUITS;
TEMPERATURE;
TEMPERATURE DISTRIBUTION;
THRESHOLD LOGIC;
TIMING CIRCUITS;
CMOS TEST CHIP;
DELAY VARIATION;
DEVELOPED MODEL;
LOW TEMPERATURES;
MATRIX ARRAYS;
RANDOM GATES;
SUBTHRESHOLD;
TEMPERATURE DEPENDENCE;
COMPUTER CIRCUITS;
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EID: 84873413383
PISSN: 15497747
EISSN: 15583791
Source Type: Journal
DOI: 10.1109/TCSII.2012.2231038 Document Type: Article |
Times cited : (9)
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References (7)
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