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Volumn 59, Issue 12, 2012, Pages 918-921

Large within-die gate delay variations in sub-threshold logic circuits at low temperature

Author keywords

Delay variations; device matrix array (DMA); sub threshold; temperature

Indexed keywords

DELAY CIRCUITS; LOGIC CIRCUITS; TEMPERATURE; TEMPERATURE DISTRIBUTION; THRESHOLD LOGIC; TIMING CIRCUITS;

EID: 84873413383     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2012.2231038     Document Type: Article
Times cited : (9)

References (7)
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  • 3
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    • The detrimental impact of negative celsius temperature on ultra-low-voltage CMOS logic
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    • Bol, D.1    Hocquet, C.2    Flandre, D.3    Legat, J.-D.4
  • 4
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    • Challenge: Variability characterization and modeling for 65- to 90-nm processes
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    • (2005) Proc. IEEE CICC, Sep. , pp. 593-599
    • Masuda, H.1    Ohkawa, S.2    Kurokawa, A.3    Aoki, M.4
  • 5
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    • Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
    • DOI 10.1109/4.52187
    • T. Sakurai and A. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE J. Solid- State Circuits, vol. 25, no. 2, pp. 584-594, Apr. 1990. (Pubitemid 20701405)
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    • Sakurai Takayasu1    Newton A.Richard2
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    • Investigation of threshold voltage variability at high temperature using Takeuchi plot
    • T. Tsunomura, A. Nishida, and T. Hiramoto, "Investigation of threshold voltage variability at high temperature using Takeuchi plot," Jpn. J. Appl. Phys., vol. 49, no. 5, pp. 054101-1-054101-6, May 2010.
    • Jpn. J. Appl. Phys. , vol.49 , Issue.5 , pp. 054101-054101
    • Tsunomura, T.1    Nishida, A.2    Hiramoto, T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.