메뉴 건너뛰기




Volumn 59, Issue 12, 2012, Pages 913-917

Ultra-low-power error correction circuits: Technology scaling and Sub-VT Operation

Author keywords

Analog decoders; biomedical implants; error correction codes (ECC); sub threshold; ultra low voltage

Indexed keywords

DECODING; ENERGY HARVESTING; IMPLANTS (SURGICAL); LOW POWER ELECTRONICS; THRESHOLD VOLTAGE; TIMING CIRCUITS;

EID: 84873410214     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2012.2231040     Document Type: Article
Times cited : (6)

References (30)
  • 1
    • 84865492858 scopus 로고    scopus 로고
    • A 5.79-Gb/s energy-efficient multirate LDPC codec chip for IEEE 802.15.3c applications
    • Sep.
    • S.-W. Yen, S.-Y. Hung, C.-L. Chen, H.-C. Chang, S.-J. Jou, and C.-Y. Lee, "A 5.79-Gb/s energy-efficient multirate LDPC codec chip for IEEE 802.15.3c applications," IEEE J. Solid-State Circuits, vol. 47, no. 9, pp. 2246-2257, Sep. 2012.
    • (2012) IEEE J. Solid-State Circuits , vol.47 , Issue.9 , pp. 2246-2257
    • Yen, S.-W.1    Hung, S.-Y.2    Chen, C.-L.3    Chang, H.-C.4    Jou, S.-J.5    Lee, C.-Y.6
  • 2
    • 77950190435 scopus 로고    scopus 로고
    • An efficient 10GBASE-T ethernet LDPC decoder design with low error floors
    • Apr
    • Z. Zhang, V. Anantharam, M. J.Wainwright, and B. Nikolic, "An efficient 10GBASE-T ethernet LDPC decoder design with low error floors," IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 843-855, Apr. 2010.
    • (2010) IEEE J. Solid-State Circuits , vol.45 , Issue.4 , pp. 843-855
    • Zhang, Z.1    Anantharam, V.2    Wainwright, M.J.3    Nikolic, B.4
  • 3
    • 77952959427 scopus 로고    scopus 로고
    • A low-complexity messagepassing algorithm for reduced routing congestion in LDPC decoders
    • May
    • T.Mohsenin, D. N. Truong, and B.M. Baas, "A low-complexity messagepassing algorithm for reduced routing congestion in LDPC decoders," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 5, pp. 1048-1061, May 2010.
    • (2010) IEEE Trans. Circuits Syst. I, Reg. Papers , vol.57 , Issue.5 , pp. 1048-1061
    • Mohsenin, T.1    Truong, D.N.2    Baas, B.M.3
  • 6
    • 33644640388 scopus 로고    scopus 로고
    • A 640-Mb/s 2048-bit programmable LDPC decoder chip
    • Mar
    • M. Mansour and N. Shanbhag, "A 640-Mb/s 2048-bit programmable LDPC decoder chip," IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 684- 698, Mar. 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.3 , pp. 684-698
    • Mansour, M.1    Shanbhag, N.2
  • 7
    • 0036504121 scopus 로고    scopus 로고
    • A 690-mW 1-Gb/s 1024-b, rate-1/2 lowdensity parity-check code decoder
    • Mar
    • A. Blanksby and C. Howland, "A 690-mW 1-Gb/s 1024-b, rate-1/2 lowdensity parity-check code decoder," IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 404-412, Mar. 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , Issue.3 , pp. 404-412
    • Blanksby, A.1    Howland, C.2
  • 8
    • 77955985782 scopus 로고    scopus 로고
    • A multiple code-rate Turbo decoder based on reciprocal dual trellis architecture
    • 30 May-Jun.
    • C.-Y. Lin, C.-C. Wong, and H.-C. Chang, "A multiple code-rate Turbo decoder based on reciprocal dual trellis architecture," in Proc. IEEE Int. Symp. Circuits Syst., 30 May-Jun. 2, 2010, pp. 1496-1499.
    • (2010) Proc. IEEE Int. Symp. Circuits Syst. , vol.2 , pp. 1496-1499
    • Lin, C.-Y.1    Wong, C.-C.2    Chang, H.-C.3
  • 10
    • 13944267907 scopus 로고    scopus 로고
    • A parallel VLSI architecture for 1-Gb/s, 2048-b, rate-1/2 Turbo Gallager code decoder
    • Sep.
    • P. Ciao, G. Colavolpe, and L. Fanucci, "A parallel VLSI architecture for 1-Gb/s, 2048-b, rate-1/2 Turbo Gallager code decoder," in Proc. Euromicro Symp. Digital Syst. Des., Sep. 2004, pp. 174-181.
    • (2004) Proc. Euromicro Symp. Digital Syst. Des. , pp. 174-181
    • Ciao, P.1    Colavolpe, G.2    Fanucci, L.3
  • 11
    • 84883587861 scopus 로고    scopus 로고
    • 125Mbps ultra-wideband system evaluation for cortical implant devices
    • Y. Luo, C. Winstead, and P. Chiang, "125Mbps ultra-wideband system evaluation for cortical implant devices," in Proc. IEEE Eng. Med. Biol. Conf., 2012, pp. 779-782.
    • (2012) Proc. IEEE Eng. Med. Biol. Conf. , pp. 779-782
    • Luo, Y.1    Winstead, C.2    Chiang, P.3
  • 12
    • 84867301723 scopus 로고    scopus 로고
    • Error correction circuits for bio-implantable electronics
    • C. Winstead and Y. Luo, "Error correction circuits for bio-implantable electronics," in Proc. IEEE Midwest Symp. Circuits Syst., 2012, pp. 158-161.
    • (2012) Proc. IEEE Midwest Symp. Circuits Syst. , pp. 158-161
    • Winstead, C.1    Luo, Y.2
  • 15
    • 0036641435 scopus 로고    scopus 로고
    • A 100-Mb/s 2.8-V CMOS current-mode analog Viterbi decoder
    • Jul
    • A. Demosthenous and J. Taylor, "A 100-Mb/s 2.8-V CMOS current-mode analog Viterbi decoder," IEEE J. Solid-State Circuits, vol. 37, no. 7, pp. 904-910, Jul. 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , Issue.7 , pp. 904-910
    • Demosthenous, A.1    Taylor, J.2
  • 17
    • 33750811602 scopus 로고    scopus 로고
    • A 0.18- CMOS analog minsum iterative decoder for a (32,8) low-density parity-check (LDPC) code
    • Nov
    • S. Hemati, A. Banihashemi, and C. Plett, "A 0.18- CMOS analog minsum iterative decoder for a (32,8) low-density parity-check (LDPC) code," IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2531-2540, Nov. 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.11 , pp. 2531-2540
    • Hemati, S.1    Banihashemi, A.2    Plett, C.3
  • 19
    • 79960881619 scopus 로고    scopus 로고
    • An analog (7,5) convolutional decoder in 65-nm CMOS for low power wireless applications
    • May
    • R. Meraji, J. B. Anderson, H. Sjoland, and V. Owall, "An analog (7,5) convolutional decoder in 65-nm CMOS for low power wireless applications," in Proc. IEEE Int. Symp. Circuits Syst., May 2011, pp. 2881-2884.
    • (2011) Proc. IEEE Int. Symp. Circuits Syst. , pp. 2881-2884
    • Meraji, R.1    Anderson, J.B.2    Sjoland, H.3    Owall, V.4
  • 20
    • 0027297425 scopus 로고
    • Near Shannon limit errorcorrecting coding and decoding: Turbo-codes. 1
    • May
    • C. Berrou, A. Glavieux, and P. Thitimajshima, "Near Shannon limit errorcorrecting coding and decoding: Turbo-codes. 1," in Proc. IEEE Int. Conf. Commun., May 1993, vol. 2, pp. 1064-1070.
    • (1993) Proc. IEEE Int. Conf. Commun. , vol.2 , pp. 1064-1070
    • Berrou, C.1    Glavieux, A.2    Thitimajshima, P.3
  • 21
    • 84925405668 scopus 로고
    • Low-density parity-check codes
    • Jan
    • R. G. Gallager, "Low-density parity-check codes," IRE Trans. Inf. Theory, vol. 8, no. 1, pp. 21-28, Jan. 1962.
    • (1962) IRE Trans. Inf. Theory , vol.8 , Issue.1 , pp. 21-28
    • Gallager, R.G.1
  • 22
    • 0031096505 scopus 로고    scopus 로고
    • Near Shannon limit performance of low density parity check codes
    • Mar
    • D. MacKay and R. Neal, "Near Shannon limit performance of low density parity check codes," Electron. Lett., vol. 33, no. 6, pp. 457-458,Mar. 1997.
    • (1997) Electron. Lett. , vol.33 , Issue.6 , pp. 457-458
    • MacKay, D.1    Neal, R.2
  • 23
    • 0030257652 scopus 로고    scopus 로고
    • Near optimum error correcting coding and decoding: Turbo-codes
    • Oct
    • C. Berrou and A. Glavieux, "Near optimum error correcting coding and decoding: Turbo-codes," IEEE Trans. Commun., vol. 44, no. 10, pp. 1261-1271, Oct. 1996.
    • (1996) IEEE Trans. Commun. , vol.44 , Issue.10 , pp. 1261-1271
    • Berrou, C.1    Glavieux, A.2
  • 25
    • 0032424528 scopus 로고    scopus 로고
    • Characterization of tissue morphology, angiogenesis, and temperature in the adaptive response of muscle tissue to chronic heating
    • Dec.
    • T. Seese, H. Arasaki, G. M. Saidel, and C. R. Davies, "Characterization of tissue morphology, angiogenesis, and temperature in the adaptive response of muscle tissue to chronic heating," Lab Invest., vol. 78, no. 12, pp. 1553-1562, Dec. 1998.
    • (1998) Lab Invest. , vol.78 , Issue.12 , pp. 1553-1562
    • Seese, T.1    Arasaki, H.2    Saidel, G.M.3    Davies, C.R.4
  • 26
    • 34047254077 scopus 로고    scopus 로고
    • A perspective on today's scaling challenges and possible future directions
    • Apr
    • R. H. Dennard, J. Cai, and A. Kumar, "A perspective on today's scaling challenges and possible future directions," Solid State Electron., vol. 51, no. 4, pp. 518-525, Apr. 2007.
    • (2007) Solid State Electron. , vol.51 , Issue.4 , pp. 518-525
    • Dennard, R.H.1    Cai, J.2    Kumar, A.3
  • 28
    • 77949584672 scopus 로고    scopus 로고
    • Scalable and low power LDPC decoder design using high level algorithmic synthesis
    • Sep.
    • Y. Sun, J. Cavallaro, and T. Ly, "Scalable and low power LDPC decoder design using high level algorithmic synthesis," in Proc. IEEE Int. SOCC, Sep. 2009, pp. 267-270.
    • (2009) Proc. IEEE Int. SOCC , pp. 267-270
    • Sun, Y.1    Cavallaro, J.2    Ly, T.3
  • 30
    • 84856491561 scopus 로고    scopus 로고
    • High-level energy estimation in the sub-VT domain: Simulation and measurement of a cardiac event detector
    • Feb
    • O. C. Akgun, J. N. Rodrigues, Y. Leblebici, and V. Owall, "High-level energy estimation in the sub-VT domain: Simulation and measurement of a cardiac event detector," IEEE Trans. Biomed. Circuits Syst., vol. 6, no. 1, pp. 15-27, Feb. 2012.
    • (2012) IEEE Trans. Biomed. Circuits Syst. , vol.6 , Issue.1 , pp. 15-27
    • Akgun, O.C.1    Rodrigues, J.N.2    Leblebici, Y.3    Owall, V.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.