Variation-tolerant architecture for ultra low power shared-L1 processor clusters

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 59, Issue 12, 2012, Pages 927-931

  Kakoee, Mohammad Reza ^a   Loi, Igor ^a   Benini, Luca ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Digital integrated circuits; reconfigurable design; system on a chip (SoC); ultra low power electronics

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; INTERCONNECTION NETWORKS (CIRCUIT SWITCHING); LOW POWER ELECTRONICS; MEMORY ARCHITECTURE; NETWORK ARCHITECTURE; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP;

EFFECT OF DELAYS; HARDWARE OVERHEADS; INTERLEAVING TECHNIQUE; PROCESSOR CLUSTER; RECONFIGURABLE DESIGNS; SYSTEM ON A CHIP; TOLERANT ARCHITECTURES; ULTRA-LOW-POWER ELECTRONICS;

PIPELINE PROCESSING SYSTEMS;

EID: 84873408154     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2012.2231039     Document Type: Article

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