Oxide liner, barrier and seed layers, and cu-plating of blind through silicon vias (TSVs) on 300mm wafers for 3D IC integration

44th International Symposium on Microelectronics 2011, IMAPS 2011

Volumn 1, Issue , 2011, Pages 1-7

  Wu, Chien Ying ^a   Chen, Shang Chun ^a   Tzeng, Pei Jer ^a   Lau, John H ^a   Hsu, Yi Feng ^a   Chen, Jui Chin ^a   Hsin, Yu Chen ^a   Chen, Chien Chou ^a   Shen, Shang Hung ^a   Lin, Cha Hsin ^a   Ku, Tzu Kun ^a   Kao, Ming Jer ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

3D IC integration; Barrier and seed layers; Cu plating; Leakage current; Oxide liner; Through silicon via (TSV)

Indexed keywords

3-D INTEGRATION; 300MM WAFER; CU-PLATING; ENABLING TECHNOLOGIES; OXIDE LINERS; SEED LAYER; THROUGH SILICON VIAS; THROUGH-SILICON-VIA (TSV);

LEAKAGE CURRENTS; MICROELECTRONICS; THREE DIMENSIONAL;

INTEGRATION;

EID: 84879988923     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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