ER: Elastic RESET for low power and long endurance MLC based phase change memory

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2012, Pages 39-44

  Jiang, Lei ^a   Zhang, Youtao ^b   Yang, Jun ^a  

^a University of Pittsburgh   (United States)

^b Learning Research and Development Ctr   (United States)

Author keywords

multi level cell; phase change memory

Indexed keywords

4-STATE; CELL STATE; ENDURANCE IMPROVEMENT; FABRICATION COST; INTERMEDIATE RESISTANCE; LOW POWER; MEMORY CAPACITY; MULTILEVEL CELL; NON-VOLATILE MEMORY TECHNOLOGY; POWER REDUCTIONS; RESET CURRENTS;

CELLS; CYTOLOGY; DATA COMPRESSION; DURABILITY; LOW POWER ELECTRONICS; PHASE CHANGE MEMORY;

ELECTRIC RESISTANCE;

EID: 84865537150     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2333660.2333672     Document Type: Conference Paper

References (24)

1. A. R. Alameldeen and D. A. Wood, "Adaptive Cache Compression for High-Performance Processors," in ISCA, 2004.
2. M. Arjomand, et al., "A Morphable PCM Architecture Considering Frequent Zero Values," in ICCD, 2011.
3. M. Awasthi, et al., "Efficient Scrub Mechanisms for Error-Prone Emerging Memories," in HPCA, 2012.
4. F. Bedeschi, et al., "A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage," JSSC, 2009.
5. S. Braga, et al., "Modeling of Partial-RESET Dynamics in Phase Change Memories," in ESSDERC, 2010.
6. S. Braga, et al., "Voltage-Driven Partial-RESET Multilevel Programming in Phase-Change Memories," in ESSDERC, 2010.
7. C. Calligaro, et al., "Comparative Analysis of Sensing Schemes for Multilevel Non-volatile Memories," in ICISS, 1997.
8. S. Cho and H. Lee, "Flip-N-Write: A Simple Deterministic Technique to Improve PRAM Write Performance, Energy and Endurance," in MICRO, 2009.
9. A. Hay, et al., "Preventing PCM Banks from Seizing Too Much Power," in MICRO, 2011.
10. L. Jiang, et al., "Enhancing Phase Change Memory Lifetime through Fine-Grained Current Regulation and Voltage Upscaling," in ISLPED, 2011.
11. L. Jiang, et al., "Improving Write Operations in MLC Phase Change Memory," in HPCA, 2012.
12. M. Joshi, et al., "Mercury: A Fast and Energy-Efficient Multi-level Cell based Phase Change Memory System," in HPCA, 2011.
13. K. Kim and S. J. Ahn, "Reliability Investigations for Manufacturable High Density PRAM," in IRPS, 2005.
14. D. Mantegazza, et al., "Statistical Analysis andModeling of Programming and Retention in PCM Arrays," in IEDM, 2007.
15. T. Nirschl, et al., "Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory," in IEDM, 2007.
16. N. Papandreou, et al., "Estimation of Amorphous Fraction in Multilevel Phase Change Memory Cells," in ESSDERC, 2009.
17. M. K. Qureshi, et al., "Enhancing Lifetime and Security of PCM-based Main Memory with Start-Gap Wear Leveling," in MICRO, 2009.
18. M. K. Qureshi, et al., "Improving Read Performance of Phase Change Memories via Write Cancellation and Write Pausing," in HPCA, 2010.
19. B. Rajendran, et al., "Analytical Model for Reset Operation of Phase Change Memory," in IEDM, 2008.
20. S. Schechter, et al., "Use ECP, not ECC, for Hard Failures in Resistive Memories," in ISCA, 2010.
21. J. Wang, et al., "Energy-efficient Multi-Level Cell PCM System with Data Encoding," in ICCD, 2011.
22. D. H. Yoon, et al., "FREE-p: Protecting Non-volatile Memory against Both Hard and Soft Errors," in HPCA, 2011.
23. W. Zhang and T. Li, "Characterizing and Mitigating the Impact of Process Variations on Phase Change based Memory Systems," in MICRO, 2009.
24. P. Zhou, et al., "A Durable and Energy Efficient Main Memory Using Phase Change Memory Technology," in ISCA, 2009.