Fine-grain voltage tuned cache architecture for yield management under process variations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 20, Issue 8, 2012, Pages 1532-1536

  Kong, Joonho ^a   Pan, Yan ^b   Ozdemir, Serkan ^c   Mohan, Anitha ^b   Memik, Gokhan ^b   Chung, Sung Woo ^a  

^a Korea University   (South Korea)

^b Northwestern University   (United States)

^c UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Cache; process variation; selective wordline voltage boosting; supply voltage lowering; yield

Indexed keywords

CACHE; PROCESS VARIATION; SUPPLY VOLTAGES; WORDLINES; YIELD;

HARDWARE;

ELECTRICAL ENGINEERING;

EID: 84862685723     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2011.2159634     Document Type: Article

References (22)

1. A. Agarwal, B. C. Paul, H. Mahmoodi, A. Datta, and K. Roy, "A process-tolerant cache architecture for improved yield in nanoscale technologies," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 1, pp. 27-38, Jan. 2005.
2. N. Azizi, F. N. Najm, and A. Moshovos, "Low-leakage asymmetriccell SRAM," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 4, pp. 701-715, Aug. 2003.
3. K. A. Bowman, S. G. Duvall, and J. D. Meindl, "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration," IEEE J. Solid-State Circuits, vol. 37, 2002.
4. G. K. Chen, D. Blaauw, T. Mudge, D. Sylvester, and N. S. Kim, "Yield-driven near-threshold SRAM design," in Proc. Int. Conf. Comput.-Aided Design (ICCAD), 2007.
5. T. Chen and S. Naffziger, "Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 5, pp. 888-899, Oct. 2003.
6. A. Das, S. Ozdemir, G. Memik, J. Zambreno, and A. N. Choudhary, "Microarchitectures for managing chip revenues under process variations," Comput. Arch. Lett., vol. 6, pp. 29-32, 2007.
7. M. Goudarzi, T. Matsumura, and T. Ishihara, "Cache power reduction in presence of within-die delay variation using spare ways," in Proc. IEEE Annu. Symp. VLSI, 2008, pp. 447-450.
8. E. P. Gusev, C. Cabral, Jr., B. P. Linder, Y. H. Kim, K. Maitra, E. Cartier, H. Nayfeh, R. Amos, G. Biery, N. Bojarczuk, A. Callegari, R. Carruthers, S. A. Cohen, M. Copel, S. Fang, M. Frank, S. Guha, M. Gribelyuk, P. Jamison, R. Jammy, M. Leong, J. Kedzierski, P. Kozlowski, V. Ku, D. Lacey, D. LaTulipe, V. Narayanan, H. Ng, P. Nguyen, J. Newbury, V. Paruchuri, R. Rengarajan, G. Shahidi, A. Steegen, M. Steen, S. Zafar, and Y. Zhang, "Advanced gate stacks with fully silicided (FUSI) gates and high-k dielectrics: Enhanced performance at reduced gate leakage," in Techn. Dig. IEDM, 2004, pp. 79-82.
9. F. Hamzaoglu, K. Zhang, Y. Wang, H. J. Ahn, U. Bhattacharya, Z. Chen, Y.-G. Ng, A. Pavlov, K. Smits, and M. Bohr, "A 153 Mb-SRAM design with dynamic stability enhancement and leakage reduction in 45 nm high-k metal-gate CMOS technology," in Proc. Int. Solid State Circuits Conf. (ISSCC), 2008, pp. 376-377.
10. C. Kim, D. Burger, and S. W. Keckler, "An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches," in Proc. Int. Conf. Arch. Support for Program. Lang. Operat. Syst. (ASPLOS), 2002, pp. 211-222.
11. C. H. Kim, J.-J. Kim, I.-J. Chang, and K. Roy, "PVT-aware leakage reduction for on-die caches with improved read stability," IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 170-178, Aug. 2006.
12. H. Lee, S. Cho, and B. R. Childers, "Exploring the interplay of yield, area, and performance in processor caches," in Proc. Int. Conf. Comput. Design (ICCD), 2007, pp. 216-223.
13. K. Meng and R. Joseph, "Process variation aware cache leakage management," in Proc. Int. Symp. Low Power Electron. Design (ISLPED), 2006, pp. 262-267.
14. B. Mohammad, S. Bijansky, A. Aziz, and J. Abraham, "Adaptive SRAM memory for low power and high yield," in Proc. Int. Conf. Comput. Design (ICCD), 2008, pp. 176-189.
15. M. Mutyam, F. Wang, R. Krishnan, V. Narayanan, M. Kandemir, Y. Xie, and M. J. Irwin, "Process variation-aware adaptive cache architecture and management," IEEE Trans. Computers, vol. 58, no. 7, pp. 865-877, Jul. 2009.
16. S. Ozdemir, D. Sinha, G. Memik, J. Adams, and H. Zhou, "Yield-aware cache architectures," in Proc. Int. Symp. Microarch. (MICRO), 2006, pp. 15-25.
17. Y. Pan, J. Kong, S. Ozdemir, G. Memik, and S. W. Chung, "Selective wordline voltage boosting for caches to manage yield under process variations," in Proc. Design Autom. Conf. (DAC), 2009, pp. 57-62.
18. M. Powell, S.-H. Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar, "Gated-: A circuit technique to reduce leakage in deep-submicron cache memories," in Proc. Int. Symp. Low Power Electron. Design (ISLPED), 2000, pp. 90-95.
19. B. F. Romanescu, M. E. Bauer, S. Ozev, and D. J. Sorin, "Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching," in Proc. ACMInt. Conf. Comput. Frontiers, 2008, pp. 129-138.
20. A. Sasan, H. Homayoun, A. Eltawil, and F. Kurdahi, "Process variation aware SRAM/cache for aggressive voltage-frequency scaling," in Proc. Design, Autom., Test Eur. (DATE), 2009, pp. 911-916.
21. P. Shivakumar, S.W. Keckler, C. R. Moore, and D. Burger, "Exploiting microarchitectural redundancy for defect tolerance," in Proc. Int. Conf. Comput. Design (ICCD), 2003, pp. 481-488.
22. J. Tschanz, K. Bowman, and V. De, "Variation-tolerant circuits: Circuit solutions and techniques," in Proc. Design Autom. Conf. (DAC), 2005, pp. 762-763.