Microarchitectures for managing chip revenues under process variations

IEEE Computer Architecture Letters

Volumn 6, Issue 2, 2007, Pages 29-32

  Das, Abhishek ^a   Ozdemir, Serkan ^a   Memik, Gokhan ^a   Zambreno, Joseph ^a   Choudhary, Alok ^a  

^a IEEE

Author keywords

Cache memories; Computer architecture; Fault tolerant computing; Process variations

Indexed keywords

BUFFER STORAGE; COMPUTER ARCHITECTURE; EARNINGS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PROFITABILITY;

FIXED PRICING MODELS; PROCESS VARIATIONS; SUBSTITUTE CACHE;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 36749081462     PISSN: 15566056     EISSN: None     Source Type: Journal    
DOI: 10.1109/L-CA.2007.8     Document Type: Article

References (13)

1. A. Agarwal, B. C. Paul, H. Mahmoodi, A. Datta, and K. Roy, "A Process-Tolerant Cache Architecture for Improved Yield in Nanoscale Technologies," IEEE Trans. Very Large Scale Integrated Systems, vol. 13, pp. 27-38, 2005.
2. AMD, "AMD Processor Pricing", May 2006, Available at http://www.amd.com/pricing
3. B. S. Amrutur and M. A. Horowitz, "Speed and Power Scaling of SRAM's," IEEE Trans. on Solid-State Circuits, vol. 35, pp. 175-1.85, Feb. 2000.
4. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, "Parameter Variations and Impact on Circuits and Microarchitectures," In Proc. of Design Automation Conference, 2003.
5. A. Datta, S. Bhunia, J. H. Choi, S. Mukhopadhyay, and K. Roy, "Speed Binning Aware Design Methodology to Improve Profit Under Parameter Variations," In Asia South Pacific Design Automation Conf., 2006.
6. P. Friedberg, Y. Cao, J. Cain, R. Wang, J. Rabaey, and C. Spanos, "Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization," In Intl. Symp. on Quality of Electronic Design, 2005.
7. E. Humenay, D. Tarjan, and K. Skadron, "Impact of Parameter Variations on Multi-Core Chips," In Proc. of Workshop on Architectural Support for Gigascale Integration, June 2006.
8. Intel, "Intel Processor Pricing", 2006, Available at http://www.intel.com/intel/finance/pricelist/processor_price_list.pdf
9. N. S. Kim, D. Blaauw, and T. Mudge, "Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches," In Proc. of Intl. Conf. on Computer Aided Design, 2003.
10. X. Liang and D. Brooks, "Mitigating the Impact of Process Variations on CPU Register File and Execution Units," In Proc. of International Symposium on Microarchitecture, 2006.
11. S. R. Nassif, "Modeling and Analysis of Manufacturing Variations," In Proc. of IEEE Conference on Custom Integrated Circuits, May 2001.
12. S. Ozdemir, D. Sinha, G. Memik, J. Adams, and H. Zhou, "Yield-Aware Cache Architectures," In Intl. Symp. on Microarchitecture, 2006.
13. Sun, "OpenSPARC T1", Available at http://opensparctl.sunsource. net/index.html